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Extract from the Register of European Patents

EP About this file: EP0250620

EP0250620 - Method and device for electrically testing printed circuits [Right-click to bookmark this link]
Former [1988/01]Method and device for testing printed circuits
[1990/36]
StatusNo opposition filed within time limit
Status updated on  06.07.1991
Database last updated on 02.09.2024
Most recent event   Tooltip01.08.2008Change - representativepublished on 03.09.2008  [2008/36]
Applicant(s)For all designated states
MANIA Elektronik Automatisation Entwicklung und Gerätebau GmbH
Technologiepark
D-61276 Weilrod / DE
[1988/19]
Former [1988/01]For all designated states
MANIA Elektronik Automatisation Entwicklung und Gerätebau GmbH
Hauptstrasse 86
D-6384 Schmitten 2 / DE
Inventor(s)01 / Driller, Hubert, Dipl.-Phys.
Altkönigstrasse 11
D-6384 Schmitten 3 / DE
02 / Mang, Paul
Weilbergstrasse 4
D-6384 Schmitten 3 / DE
[1988/01]
Representative(s)Ruschke, Hans Edvard, et al
Ruschke Madgwick Seide & Kollegen
Patentanwälte Patent Attorney (UK) PartG mbB
Postfach 86 06 29
81633 München / DE
[N/P]
Former [2008/36]Ruschke, Hans Edvard, et al
RUSCHKE HARTMANN MADGWICK & SEIDE Patent- und Rechtsanwälte Postfach 86 06 29
81633 München / DE
Former [1988/01]Ruschke, Hans Edvard, et al
Patentanwälte Ruschke, Lewald, Hartmann & Partner Pienzenauerstrasse 2
D-81679 München / DE
Application number, filing date86108680.925.06.1986
[1988/01]
Filing languageDE
Procedural languageDE
PublicationType: A1 Application with search report 
No.:EP0250620
Date:07.01.1988
Language:DE
[1988/01]
Type: B1 Patent specification 
No.:EP0250620
Date:05.09.1990
Language:DE
[1990/36]
Search report(s)(Supplementary) European search report - dispatched on:EP24.03.1987
ClassificationIPC:G01R31/28, G01R1/073
[1988/01]
CPC:
G01R1/073 (EP,US); G01R31/281 (EP,US)
Designated contracting statesAT,   BE,   CH,   DE,   FR,   GB,   IT,   LI,   LU,   NL,   SE [1988/01]
TitleGerman:Verfahren und Vorrichtung zum elektrischen Prüfen von Leiterplatten[1990/36]
English:Method and device for electrically testing printed circuits[1990/36]
French:Procédé et dispositif pour tester électriquement des circuits imprimés[1990/36]
Former [1988/01]Verfahren und Vorrichtung zum Prüfen von Leiterplatten
Former [1988/01]Method and device for testing printed circuits
Former [1988/01]Procédé et dispositif pour tester des circuits imprimés
Examination procedure30.06.1987Examination requested  [1988/01]
08.04.1988Despatch of a communication from the examining division (Time limit: M06)
18.10.1988Reply to a communication from the examining division
01.12.1988Despatch of a communication from the examining division (Time limit: M04)
05.04.1989Reply to a communication from the examining division
26.06.1989Despatch of communication of intention to grant (Approval: Yes)
21.02.1990Communication of intention to grant the patent
24.04.1990Fee for grant paid
24.04.1990Fee for publishing/printing paid
Opposition(s)06.06.1991No opposition filed within time limit [1991/35]
Fees paidRenewal fee
24.06.1988Renewal fee patent year 03
27.10.1989Renewal fee patent year 04
28.06.1990Renewal fee patent year 05
Penalty fee
Additional fee for renewal fee
01.07.198904   M06   Fee paid on   27.10.1989
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipSE05.09.1990
[1991/27]
Documents cited:Search[A]DE2013070  (LICENTIA GMBH);
 [X]DE2707900  (MILKOVIC ANTE);
 [A]US4321533  (MATRONE JOHN L);
 [A]US4471298  (FROHLICH SIGURD [US]);
 [A]DE3524229  (INGUN PRUEFMITTELBAU [DE])
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.