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EP0257120
European procedure
Extract from the Register of European Patents
EP About this file: EP0257120
| EP0257120 - Decoding method and circuit arrangement for a redundant CMOS semiconductor memory [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 09.04.1993 Database last updated on 28.06.2024 | Most recent event Tooltip | 09.04.1993 | No opposition filed within time limit | published on 02.06.1993 [1993/22] | Applicant(s) | For all designated states International Business Machines Corporation New Orchard Road Armonk, NY 10504 / US | [N/P] |
| Former [1988/09] | For all designated states International Business Machines Corporation Old Orchard Road Armonk, N.Y. 10504 / US | Inventor(s) | 01 /
Loehlein, W.D., Elektro-Ing. Goldregenstrasse 2 D-7033 Herrenberg / DE | 02 /
Tong, M.H., Dipl.-Ing. Rhönweg 22B D-7030 Böblingen / DE | 03 /
Helwig, K. Dipl.-Ing. Richard Wagner Strasse 23 D-7032 Sindelfingen / DE | [1988/09] | Representative(s) | Mönig, Anton IBM Deutschland Informationssysteme GmbH, Patentwesen und Urheberrecht 70548 Stuttgart / DE | [N/P] |
| Former [1993/19] | Mönig, Anton, Dipl.-Ing. IBM Deutschland Informationssysteme GmbH, Patentwesen und Urheberrecht D-70548 Stuttgart / DE | ||
| Former [1993/13] | Mönig, Anton, Dipl.-Ing. IBM Deutschland Informationssysteme GmbH Patentwesen und Urheberrecht Pascalstrasse 100 W-7000 Stuttgart 80 / DE | ||
| Former [1988/09] | Rudolph, Wolfgang, Dipl.-Ing. IBM Deutschland GmbH Schönaicher Strasse 220 D-7030 Böblingen / DE | Application number, filing date | 86111646.5 | 22.08.1986 | [1988/09] | Filing language | DE | Procedural language | DE | Publication | Type: | A1 Application with search report | No.: | EP0257120 | Date: | 02.03.1988 | Language: | DE | [1988/09] | Type: | B1 Patent specification | No.: | EP0257120 | Date: | 10.06.1992 | Language: | DE | [1992/24] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 25.05.1987 | Classification | IPC: | G06F11/20 | [1988/09] | CPC: |
G11C29/83 (EP,US);
G11C29/84 (EP,US)
| Designated contracting states | DE, FR, GB [1988/09] | Title | German: | Dekodierverfahren und -Schaltungsanordnung für einen redundanten CMOS-Halbleiterspeicher | [1988/09] | English: | Decoding method and circuit arrangement for a redundant CMOS semiconductor memory | [1988/09] | French: | Procédé et circuit de décodage pour une mémoire redondante à semi-conducteurs CMOS | [1988/09] | Examination procedure | 16.06.1988 | Examination requested [1988/33] | 20.09.1990 | Despatch of a communication from the examining division (Time limit: M06) | 20.03.1991 | Reply to a communication from the examining division | 19.07.1991 | Despatch of communication of intention to grant (Approval: No) | 14.11.1991 | Despatch of communication of intention to grant (Approval: later approval) | 05.12.1991 | Communication of intention to grant the patent | 11.12.1991 | Fee for grant paid | 11.12.1991 | Fee for publishing/printing paid | Opposition(s) | 11.03.1993 | No opposition filed within time limit [1993/22] | Fees paid | Renewal fee | 23.08.1988 | Renewal fee patent year 03 | 21.08.1989 | Renewal fee patent year 04 | 20.08.1990 | Renewal fee patent year 05 | 22.08.1991 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]EP0029322 (FUJITSU LTD [JP]); | [A]GB2165378 (HITACHI LTD); | [A]EP0155829 (MITSUBISHI ELECTRIC CORP [JP]) |