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Extract from the Register of European Patents

EP About this file: EP0201205

EP0201205 - Apparatus and methods for semiconductor wafer testing [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  07.09.1991
Database last updated on 11.09.2024
Most recent event   Tooltip23.11.2007Lapse of the patent in a contracting state
Updated state(s): FR		published on 26.12.2007  [2007/52]
Applicant(s)For all designated states
PROMETRIX CORPORATION
3255 Scott Boulevard Building 2 Suite A Santa Clara
California 95054 / US
[N/P]
Former [1986/46]For all designated states
PROMETRIX CORPORATION
3255 Scott Boulevard Building 2 Suite A
Santa Clara California 95054 / US
Inventor(s)01 / Mallory, Chester
1073 Lucot Way
Campbell California 95008 / US
02 / Perloff, David Steven
1089 Valley Forge Drive
Sunnyvale California 94087 / US
03 / Hung, Van Pham
1753 Daltrey Way
San Jose California 95132 / US
04 / Droblisch, Sandor
15362 Elm Park
Monte Sereno California 95030 / US
[1986/46]
Representative(s)Bayliss, Geoffrey Cyril, et al
BOULT WADE TENNANT
Verulam Gardens
70 Gray's Inn Road
London WC1X 8BT / GB
[N/P]
Former [1986/46]Bayliss, Geoffrey Cyril, et al
BOULT, WADE & TENNANT 27 Furnival Street
London EC4A 1PQ / GB
Application number, filing date86302565.607.04.1986
[1986/46]
Priority number, dateUS1985072649824.04.1985         Original published format: US 726498
[1986/46]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP0201205
Date:04.02.1987
Language:EN
[1987/06]
Type: A3 Search report 
No.:EP0201205
Date:04.02.1987
Language:EN
[1987/06]
Type: B1 Patent specification 
No.:EP0201205
Date:07.11.1990
Language:EN
[1990/45]
Search report(s)(Supplementary) European search report - dispatched on:EP15.09.1986
ClassificationIPC:G01R31/28, H05K13/02, H05K13/00
[1986/46]
CPC:
G01R31/2831 (EP,US); H01L21/68 (EP,US)
Designated contracting statesAT,   BE,   CH,   DE,   FR,   GB,   IT,   LI,   LU,   NL,   SE [1986/46]
TitleGerman:Gerät und Verfahren zur Prüfung von Halbleiterchips[1986/46]
English:Apparatus and methods for semiconductor wafer testing[1986/46]
French:Appareil et procédé pour tester des plaquettes semi-conductrices[1986/46]
File destroyed:15.01.2000
Examination procedure13.12.1986Examination requested  [1987/06]
02.05.1989Despatch of a communication from the examining division (Time limit: M04)
19.08.1989Reply to a communication from the examining division
28.09.1989Despatch of a communication from the examining division (Time limit: M04)
16.01.1990Reply to a communication from the examining division
22.03.1990Despatch of communication of intention to grant (Approval: Yes)
10.05.1990Communication of intention to grant the patent
31.07.1990Fee for grant paid
31.07.1990Fee for publishing/printing paid
Opposition(s)08.08.1991No opposition filed within time limit [1991/44]
Fees paidRenewal fee
05.04.1988Renewal fee patent year 03
27.04.1989Renewal fee patent year 04
09.04.1990Renewal fee patent year 05
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipAT07.11.1990
BE07.11.1990
CH07.11.1990
FR07.11.1990
IT07.11.1990
LI07.11.1990
NL07.11.1990
SE07.11.1990
LU30.04.1991
[2006/14]
Former [1999/52]AT07.11.1990
BE07.11.1990
CH07.11.1990
IT07.11.1990
LI07.11.1990
NL07.11.1990
SE07.11.1990
FR29.03.1991
LU30.04.1991
Former [1999/42]AT07.11.1990
BE07.11.1990
CH07.11.1990
IT07.11.1990
LI07.11.1990
NL07.11.1990
SE07.11.1990
FR29.03.1991
Former [1991/50]AT07.11.1990
BE07.11.1990
CH07.11.1990
LI07.11.1990
NL07.11.1990
SE07.11.1990
FR29.03.1991
Former [1991/45]AT07.11.1990
BE07.11.1990
CH07.11.1990
LI07.11.1990
NL07.11.1990
SE07.11.1990
Former [1991/42]AT07.11.1990
BE07.11.1990
CH07.11.1990
LI07.11.1990
SE07.11.1990
Former [1991/38]BE07.11.1990
SE07.11.1990
Former [1991/27]SE07.11.1990
Documents cited:Search[A]US4328553  (FREDRIKSEN THORBJOERN R, et al)
 [Y]  - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 17, no. 3, August 1974, page 880-881, New York, US; R.E. HOGAN et al.: "Precision mechanism for use in a system requiring precise alignment"
 [Y]  - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 21, no. 10, March 1979, pages 4086-4087, IBM Corp., New York, US; W. SCHWARZ: "Rotatable wafer chuck for testing"
 [A]  - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 17, no. 8, January 1975, pages 2220-2221, New York, US; M. GAGNE: "No-edge contact wafer orientor"
ExaminationUS4204155
 US4703252
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.