-
EP0204499
European procedure
- EP About this file
- EP Legal status
- EP Federated register
- EP Event history
- EP Citations
- EP Patent family
- EP All documents
Extract from the Register of European Patents
EP About this file: EP0204499
| EP0204499 - High voltage isolation circuit for CMOS networks [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 28.08.1992 Database last updated on 02.11.2024 | Most recent event Tooltip | 07.07.2007 | Change - inventor | published on 08.08.2007 [2007/32] | Applicant(s) | For all designated states ADVANCED MICRO DEVICES, INC. 901 Thompson Place P.O. Box 3453 Sunnyvale CA 94088-3453 / US | [N/P] |
| Former [1986/50] | For all designated states ADVANCED MICRO DEVICES, INC. 901 Thompson Place P.O. Box 3453 Sunnyvale, CA 94088 / US | Inventor(s) | 01 /
Venkatesh, Bhimachar 460 Roosevelt Avenue Sunnyvale California / US | [1986/50] | Representative(s) | Wright, Hugh Ronald, et al Brookes Batchellor LLP 1 Boyne Park Tunbridge Wells Kent TN4 8EL / GB | [N/P] |
| Former [1986/50] | Wright, Hugh Ronald, et al Brookes & Martin 52/54 High Holborn London WC1V 6SE / GB | Application number, filing date | 86304039.0 | 28.05.1986 | [1986/50] | Priority number, date | US19850738925 | 29.05.1985 Original published format: US 738925 | [1986/50] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0204499 | Date: | 10.12.1986 | Language: | EN | [1986/50] | Type: | A3 Search report | No.: | EP0204499 | Date: | 14.12.1988 | Language: | EN | [1988/50] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 24.10.1988 | Classification | IPC: | H03K19/017, H03K19/003 | [1986/50] | CPC: |
H03K19/00315 (EP,US);
H03K19/01721 (EP,US)
| Designated contracting states | AT, BE, CH, DE, FR, GB, IT, LI, LU, NL, SE [1986/50] | Title | German: | Hochspannungsisolierungsschaltung für CMOS-Netzwerke | [1986/50] | English: | High voltage isolation circuit for CMOS networks | [1986/50] | French: | Circuit d'isolation haute tension pour réseaux CMOS | [1986/50] | File destroyed: | 12.06.1999 | Examination procedure | 27.02.1989 | Examination requested [1989/17] | 23.10.1990 | Despatch of a communication from the examining division (Time limit: M04) | 07.01.1991 | Reply to a communication from the examining division | 29.01.1991 | Despatch of a communication from the examining division (Time limit: M04) | 28.03.1991 | Reply to a communication from the examining division | 04.11.1991 | Despatch of communication of intention to grant (Approval: Yes) | 10.01.1992 | Communication of intention to grant the patent | 22.04.1992 | Application deemed to be withdrawn, date of legal effect [1992/43] | 22.05.1992 | Despatch of communication that the application is deemed to be withdrawn, reason: fee for grant / fee for printing not paid in time [1992/43] | Fees paid | Renewal fee | 19.05.1988 | Renewal fee patent year 03 | 28.05.1989 | Renewal fee patent year 04 | 22.05.1990 | Renewal fee patent year 05 | 19.12.1990 | Renewal fee patent year 06 | Penalty fee | Additional fee for renewal fee | 01.06.1992 | 07 M06 Not yet paid |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [Y]US4511811 (GUPTA ANIL [US]); | [Y]US4442481 (BRAHMBHATT DHAVAL J [US]); | [A]EP0136771 (TOSHIBA KK [JP]); | [A]EP0090116 (FUJITSU LTD [JP]) | [Y] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 26, no. 10A, March 1984, pages 5296-5298, New York, US; A.H. TABER: "Circuit technique to help prevent CMOS latch-up" |