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EP0231583
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EP About this file: EP0231583
| EP0231583 - CMOS programmable logic array [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 20.06.1991 Database last updated on 18.11.2024 | Most recent event Tooltip | 07.07.2007 | Change - inventor | published on 08.08.2007 [2007/32] | Applicant(s) | For all designated states AMERICAN MICROSYSTEMS, INCORPORATED 3800 Homestead Road Santa Clara, CA 95051 / US | [1987/33] | Inventor(s) | 01 /
Jochem, Daniel R. 2770 Kootenai Pocatello Idaho 83201 / US | [1987/33] | Representative(s) | Crawford, Andrew Birkby, et al A.A. Thornton & Co. 235 High Holborn London WC1V 7LE / GB | [N/P] |
| Former [1989/15] | Crawford, Andrew Birkby, et al A.A. THORNTON & CO. Northumberland House 303-306 High Holborn London WC1V 7LE / GB | ||
| Former [1987/33] | Barrett, James William A.A. THORNTON & CO. Northumberland House 303-306 High Holborn London WC1V 7LE / GB | Application number, filing date | 86307482.9 | 30.09.1986 | [1987/33] | Priority number, date | US19850787234 | 15.10.1985 Original published format: US 787234 | [1987/33] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0231583 | Date: | 12.08.1987 | Language: | EN | [1987/33] | Type: | A3 Search report | No.: | EP0231583 | Date: | 25.01.1989 | Language: | EN | [1989/04] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 06.12.1988 | Classification | IPC: | H03K19/177 | [1987/33] | CPC: |
H03K19/0013 (EP,US);
H03K19/1772 (EP,US)
| Designated contracting states | AT, DE, FR, GB, NL [1987/33] | Title | German: | CMOS-programmierbare logische Anordnung | [1987/33] | English: | CMOS programmable logic array | [1987/33] | French: | Réseau logique programmable CMOS | [1987/33] | File destroyed: | 02.03.1998 | Examination procedure | 02.03.1989 | Examination requested [1989/19] | 25.09.1990 | Despatch of a communication from the examining division (Time limit: M04) | 06.02.1991 | Application deemed to be withdrawn, date of legal effect [1991/32] | 13.03.1991 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time [1991/32] | Fees paid | Renewal fee | 22.08.1988 | Renewal fee patent year 03 | 23.08.1989 | Renewal fee patent year 04 | Penalty fee | Additional fee for renewal fee | 01.10.1990 | 05 M06 Not yet paid |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]JP5947845 ; | [AP]JP61101124 ; | [A]GB2032663 (IBM); | [AP]US4611133 (PETERSON BENJAMIN C [US], et al); | [A]US4183093 (KAWAGOE HIROTO [JP]) | [A] - PATENT ABSTRACTS OF JAPAN, vol. 8, no. 139 (E-253)[1576], 28th June 1984; & JP-A-59 47 845 (NIPPON DENKI K.K.) 17-03-1984, & JP5947845 A 00000000 | [AP] - PATENT ABSTRACTS OF JAPAN, vol. 10, no. 183 (E-440)[2339], 26th September 1986, page 44 E 440; & JP-A-61 101 124 (HITACHI MICRO COMPUT ENG LTD) 20-05-1986, & JP61101124 A 00000000 | [A] - IEEE TRANSACTIONS ON MAGNETICS, vol. SC19, no. 6, December 1984, pages 1041-1043, IEEE, New York, US; E. FONG et al.: "An electrically reconfigurable programmable logic array using a CMOS/DMOS technology" | [A] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 20, no. 4, September 1977, pages 1640-1643, New York, US; P.W. COOK et al.: "Programmable logic arrays using polysilicon-gate FETS" |