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Extract from the Register of European Patents

EP About this file: EP0226433

EP0226433 - High density printed wiring board [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  29.12.1990
Database last updated on 05.10.2024
Most recent event   Tooltip29.12.1990No opposition filed within time limitpublished on 20.02.1991 [1991/08]
Applicant(s)For all designated states
FUJITSU LIMITED
1015, Kamikodanaka, Nakahara-ku Kawasaki-shi
Kanagawa 211 / JP
[N/P]
Former [1987/26]For all designated states
FUJITSU LIMITED
1015, Kamikodanaka, Nakahara-ku
Kawasaki-shi, Kanagawa 211 / JP
Inventor(s)01 / Seyama, Kiyotaka Fujitsu Ltd Patent Department
Kosugi Fujitsu Bldg 1812-10 Shimonumabe
Nakahara-ku Kawasaki-shi Kanagawa 211 / JP
[1987/26]
Representative(s)Billington, Lawrence Emlyn, et al
Haseltine Lake LLP Lincoln House, 5th Floor 300 High Holborn
London WC1V 7JH / GB
[N/P]
Former [1987/26]Billington, Lawrence Emlyn, et al
HASELTINE LAKE & CO Hazlitt House 28 Southampton Buildings Chancery Lane
London WC2A 1AT / GB
Application number, filing date86309571.709.12.1986
[1987/26]
Priority number, dateJP1985027758009.12.1985         Original published format: JP 27758085
[1987/26]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0226433
Date:24.06.1987
Language:EN
[1987/26]
Type: A3 Search report 
No.:EP0226433
Date:02.09.1987
Language:EN
[1987/36]
Type: B1 Patent specification 
No.:EP0226433
Date:07.03.1990
Language:EN
[1990/10]
Search report(s)(Supplementary) European search report - dispatched on:EP16.07.1987
ClassificationIPC:H05K1/00, H05K1/11, H01L23/52
[1987/26]
CPC:
H05K1/0292 (EP,US); H01L23/5384 (EP,US); H05K1/114 (EP,US);
H01L2224/16225 (EP,US); H05K1/0298 (EP,US); H05K2201/10704 (EP,US);
H05K2201/10719 (EP,US); H05K2201/10734 (EP,US); H05K3/429 (EP,US);
Y10T29/49156 (EP,US) (-)
Designated contracting statesDE,   ES,   GB [1987/26]
TitleGerman:Gedruckte Schaltungsplatte mit hoher Dichte[1987/26]
English:High density printed wiring board[1987/26]
French:Circuit imprimé à haute densité[1987/26]
Examination procedure13.01.1988Examination requested  [1988/11]
15.06.1988Despatch of a communication from the examining division (Time limit: M06)
22.10.1988Reply to a communication from the examining division
08.02.1989Despatch of communication of intention to grant (Approval: Yes)
02.06.1989Communication of intention to grant the patent
25.07.1989Fee for grant paid
25.07.1989Fee for publishing/printing paid
Opposition(s)08.12.1990No opposition filed within time limit [1991/08]
Fees paidRenewal fee
30.11.1988Renewal fee patent year 03
07.12.1989Renewal fee patent year 04
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Documents cited:Search[A]US4521449  (ARNOLD ANTHONY F [US], et al);
 [A]US4016463  (BEALL ROBERT J, et al)
 [X]  - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 27, no. 2, July 1984, pages 1201,1202, New York, US; R.A. MAGEE et al.: "Pinned multilayer ceramic substrate"
 [Y]  - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 21, no. 11, April 1979, pages 4491,4492, New York, US; M.R. MARASCH et al.:"Dual-purpose bonding pads for semiconductor package substrates"
 [A]  - ELEKTRONIK, vol. 29, no. 21, Oktober 1980, pages 125-128, Munich, DE; H. KRUMM: "Bessere Leiterplattenausnutzung mit neuem Mehrchip-IC-Gehäuse"
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.