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EP0204612
European procedure
Extract from the Register of European Patents
EP About this file: EP0204612
| EP0204612 - Method for transmitting data with a possibility for packet error correction, and coding and decoding apparatus for carrying out said method [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 06.06.1991 Database last updated on 05.10.2024 | Most recent event Tooltip | 06.06.1991 | No opposition filed within time limit | published on 24.07.1991 [1991/30] | Applicant(s) | For all designated states LABORATOIRE CENTRAL DE TELECOMMUNICATIONS Société anonyme: 18-20, rue Grange-Dame-Rose 78140 Velizy Villacoublay / FR | [N/P] |
| Former [1986/50] | For all designated states LABORATOIRE CENTRAL DE TELECOMMUNICATIONS Société anonyme: 18-20, rue Grange-Dame-Rose F-78140 Velizy Villacoublay / FR | Inventor(s) | 01 /
Dornstetter, Jean-Louis 13, rue du Général Pershing F-78000 Versailles / FR | [1986/50] | Representative(s) | Ballot, Paul Denis Jacques Cabinet Ballot 122, rue Edouard Vaillant 92593 Levallois-Perret Cedex / FR | [N/P] |
| Former [1988/23] | Ballot, Paul Denis Jacques Cabinet Ballot-Schmit, 7, rue Le Sueur F-75116 Paris / FR | ||
| Former [1986/50] | Albert, Claude L C T Boîte postale 40 F-78141 Vélizy-Villacoublay Cédex / FR | Application number, filing date | 86401109.3 | 27.05.1986 | [1986/50] | Priority number, date | FR19850008098 | 30.05.1985 Original published format: FR 8508098 | [1986/50] | Filing language | FR | Procedural language | FR | Publication | Type: | A1 Application with search report | No.: | EP0204612 | Date: | 10.12.1986 | Language: | FR | [1986/50] | Type: | B1 Patent specification | No.: | EP0204612 | Date: | 01.08.1990 | Language: | FR | [1990/31] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 30.09.1986 | Classification | IPC: | H03M13/00, G06F11/10 | [1986/50] | CPC: |
H03M13/151 (EP,US)
| Designated contracting states | AT, BE, CH, DE, GB, IT, LI, NL, SE [1986/50] | Title | German: | Verfahren zur Datenübertragung mit Möglichkeit zur Korrektur von Fehlerpaketen und Kodierungs- und Dekodierungsanordnung zur Durchführung dieses Verfahrens | [1986/50] | English: | Method for transmitting data with a possibility for packet error correction, and coding and decoding apparatus for carrying out said method | [1986/50] | French: | Procédé de transmission, avec possibilité de correction de paquets d'erreurs, de messages d'information et dispositifs de codage et de décodage pour la mise en oeuvre de ce procédé | [1986/50] | Examination procedure | 14.05.1987 | Examination requested [1987/29] | 13.02.1989 | Despatch of a communication from the examining division (Time limit: M06) | 11.08.1989 | Reply to a communication from the examining division | 22.12.1989 | Despatch of communication of intention to grant (Approval: Yes) | 05.02.1990 | Communication of intention to grant the patent | 08.03.1990 | Fee for grant paid | 08.03.1990 | Fee for publishing/printing paid | Opposition(s) | 03.05.1991 | No opposition filed within time limit [1991/30] | Fees paid | Renewal fee | 25.04.1988 | Renewal fee patent year 03 | 20.04.1989 | Renewal fee patent year 04 | 23.04.1990 | Renewal fee patent year 05 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]WO8100316 (CYCLOTOMICS INC); | [A]WO8501625 (CYCLOTOMICS INC [US]) | [A] - ARCHIV FÜR ELEKTRONIK UND ÜBERTRAGUNGSTECHNIK, vol. 38, no. 5, septembre/octobre 1984, pages 281-289, Würzburg, DE; M. PRÖGLER et al.: "Realisierung algebraischer Fehlerkorrektur mit Standard-Mikrorechnern" | [A] - IEEE TRANSACTIONS ON INFORMATIONS THEORY, vol. IT-19, no. 5, septembre 1973, pages 590-592, New York, US; E.R. BERLEKAMP: "Goppa codes" | [A] - IEEE TRANSACTIONS ON COMPUTERS, vol. C-33, no. 2, février 1984, pages 178-189, IEEE, New York, US; KUANG YUNG LIU: "Architecture for VLSI design of reed-solomon decoders" | [A] - THE TRANSACTIONS OF THE IECE OF JAPAN, vol. E-64, no. 10, octobre 1981, pages 653-660, Tokyo, JP; E. FUJIWARA et al.: "Fault-tolerant arithmetic logic unit using parity-based codes" |