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EP0216851
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Extract from the Register of European Patents
EP About this file: EP0216851
| EP0216851 - COMPLEMENTARY FET DELAY/LOGIC CELL [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 07.02.1989 Database last updated on 03.09.2024 | Most recent event Tooltip | 07.07.2007 | Change - inventor | published on 08.08.2007 [2007/32] | Applicant(s) | For all designated states AT&T Corp. 32 Avenue of the Americas New York, NY 10013-2412 / US | [1987/15] | Inventor(s) | 01 /
DIMYAN, Magid, Yousri 520 North 27th Street Allentown, Pennsylvania / US | 02 /
JOSEPH, Saul, Joshua 2315 Pewter Drive Macungie, PA 18062 / US | 03 /
KRAKOW, William, Tompkins 706 Emory Drive Chapel Hill, NC 27514 / US | 04 /
PEDERSEN, Richard, Alan R.D. 2 Box 190-4 New Tripoli, PA 18066 / US | [1987/15] | Representative(s) | Buckley, Christopher Simon Thirsk, et al Lucent Technologies Inc., 5 Mornington Road Woodford Green Essex IG8 0TU / GB | [N/P] |
| Former [1987/15] | Buckley, Christopher Simon Thirsk, et al AT&T (UK) Ltd. 5 Mornington Road Woodford Green Essex IG8 0TU / GB | Application number, filing date | 86902099.0 | 25.02.1986 | [1987/15] | WO1986US00412 | Priority number, date | US19850716357 | 26.03.1985 Original published format: US 716357 | [1987/15] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | WO8605935 | Date: | 09.10.1986 | Language: | EN | [1986/22] | Type: | A1 Application with search report | No.: | EP0216851 | Date: | 08.04.1987 | Language: | EN | The application published by WIPO in one of the EPO official languages on 09.10.1986 takes the place of the publication of the European patent application. | [1987/15] | Search report(s) | International search report - published on: | EP | 09.10.1986 | Classification | IPC: | H03K19/096 | [1987/15] | CPC: |
H03K19/00 (KR);
H03K19/0963 (EP)
| Designated contracting states | DE, GB, IT [1987/20] |
| Former [1987/15] | AT, BE, CH, DE, FR, GB, IT, LI, LU, NL, SE | Title | German: | KOMPLEMENTÄRE FET-VERZÖGERUNGS/LOGIK-ZELLE | [1987/15] | English: | COMPLEMENTARY FET DELAY/LOGIC CELL | [1987/15] | French: | CELLULE LOGIQUE/DE RETARD A TRANSISTOR A EFFET DE CHAMP COMPLEMENTAIRE | [1987/15] | File destroyed: | 08.05.1995 | Entry into regional phase | 18.11.1986 | National basic fee paid | 18.11.1986 | Designation fee(s) paid | Examination procedure | 10.04.1987 | Application deemed to be withdrawn, date of legal effect [1989/13] | 28.09.1988 | Despatch of communication that the application is deemed to be withdrawn, reason: examination fee not paid in time [1989/13] | Fees paid | Penalty fee | Penalty fee Rule 85b EPC 1973 | 09.04.1987 | M02 Not yet paid | Additional fee for renewal fee | 29.02.1988 | 03 M06 Not yet paid |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Cited in | International search | US3675144 [ ] (ZUK BORYS); | US4122360 [ ] (KAWAGAI KENJI, et al); | US3937982 [ ] (NAKAJIMA TOSHIO) | [A] - IEEE Transactions on Computers, Vol. C-33, No. 7, July 1984 (New York, US) R.R. SHIVELY et al.: "Cascading Transmission gates to Enhance Multiplier Performance", pages 677-679, see page 678, figure 1; left-hand columnlines 30-68 (cited in the application) |