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EP0239746
European procedure
Extract from the Register of European Patents
EP About this file: EP0239746
| EP0239746 - Method for manufacturing a semiconductor device [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 02.03.1995 Database last updated on 07.10.2024 | Most recent event Tooltip | 02.03.1995 | No opposition filed within time limit | published on 19.04.1995 [1995/16] | Applicant(s) | For all designated states Kabushiki Kaisha Toshiba 72, Horikawa-cho, Saiwai-ku Kawasaki-shi Kanagawa-ken 210-8572 / JP | [N/P] |
| Former [1987/41] | For all designated states KABUSHIKI KAISHA TOSHIBA 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210, Tokyo / JP | Inventor(s) | 01 /
Nagakubo, Yoshihide Patent Div. K.K. Toshiba 1-1 Shibaura 1-chome Minato-ku Tokyo 105 / JP | [1987/41] | Representative(s) | Lehn, Werner, et al Hoffmann Eitle, Patent- und Rechtsanwälte, Postfach 81 04 20 81904 München / DE | [N/P] |
| Former [1987/41] | Lehn, Werner, Dipl.-Ing., et al Hoffmann, Eitle & Partner, Patentanwälte, Postfach 81 04 20 D-81904 München / DE | Application number, filing date | 87101503.8 | 04.02.1987 | [1987/41] | Priority number, date | JP19860032697 | 19.02.1986 Original published format: JP 3269786 | [1987/41] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0239746 | Date: | 07.10.1987 | Language: | EN | [1987/41] | Type: | A3 Search report | No.: | EP0239746 | Date: | 23.11.1989 | Language: | EN | [1989/47] | Type: | B1 Patent specification | No.: | EP0239746 | Date: | 27.04.1994 | Language: | EN | [1994/17] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 02.10.1989 | Classification | IPC: | H01L21/205, H01L21/306, H01L21/86, H01L21/3205 | [1994/17] | CPC: |
H01L21/4846 (EP,US);
H01L21/86 (EP,US);
H01L23/4825 (EP,US);
H01L2924/0002 (EP,US);
Y10S148/15 (EP,US)
| C-Set: |
H01L2924/0002, H01L2924/00 (EP,US)
|
| Former IPC [1989/49] | H01L21/205, H01L21/306, H01L21/86 | ||
| Former IPC [1987/41] | H01L21/205, H01L21/306 | Designated contracting states | DE, FR, GB [1987/41] | Title | German: | Verfahren zur Herstellung von Halbleiterbauelementen | [1987/41] | English: | Method for manufacturing a semiconductor device | [1987/41] | French: | Procédé de fabrication de dispositif à semi-conducteur | [1987/41] | Examination procedure | 04.02.1987 | Examination requested [1987/41] | 26.05.1992 | Despatch of a communication from the examining division (Time limit: M06) | 25.11.1992 | Reply to a communication from the examining division | 11.12.1992 | Despatch of a communication from the examining division (Time limit: M02) | 19.02.1993 | Reply to a communication from the examining division | 31.03.1993 | Despatch of communication of intention to grant (Approval: Yes) | 04.08.1993 | Communication of intention to grant the patent | 26.10.1993 | Fee for grant paid | 26.10.1993 | Fee for publishing/printing paid | Opposition(s) | 28.01.1995 | No opposition filed within time limit [1995/16] | Fees paid | Renewal fee | 10.02.1989 | Renewal fee patent year 03 | 14.02.1990 | Renewal fee patent year 04 | 17.12.1990 | Renewal fee patent year 05 | 10.02.1992 | Renewal fee patent year 06 | 08.02.1993 | Renewal fee patent year 07 | 08.02.1994 | Renewal fee patent year 08 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]EP0049400 (TOKYO SHIBAURA ELECTRIC CO [JP]); | [A]US4348804 (OGAWA MITSURU, et al); | [AP]EP0191981 (MARCONI ELECTRONIC DEVICES [GB]) | [A] - IEEE JOURNAL OF SOLID-STATE CIRCUITS vol. SC-11, no. 2, April 1976, pages 329-336; A.C. IPRI et al.: "Low-Threshold Low-Power CMOS/SOS for High-Frequency Counter Applictions" | [A] - IEEE TRANSACTIONS ON NUCLEAR SCIENCE vol. NS-24, no. 6, December 1977, pages 2205-2208; S. N. LEE et al.: "Radiation-Hardened Silicon-Gate SMOS/SOS" |