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Extract from the Register of European Patents

EP About this file: EP0257277

EP0257277 - Method for simultaneously forming a interconnection level and via studs [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  23.07.1992
Database last updated on 01.10.2024
Most recent event   Tooltip07.07.2007Change - inventorpublished on 08.08.2007  [2007/32]
Applicant(s)For all designated states
International Business Machines Corporation
New Orchard Road
Armonk, NY 10504 / US
[N/P]
Former [1988/09]For all designated states
International Business Machines Corporation
Old Orchard Road
Armonk, N.Y. 10504 / US
Inventor(s)01 / Chalou, Paul Normand Jr.
68 Balfour Drive
Wappingers Falls, NY 12590 / US
02 / Houghton, Thomas Frederick
24 Birch Drive
Beacon, NY 12508 / US
03 / West, Richard Keith
11 Westview Terrace
Poughkeepsie, NY 12603 / US
[1988/09]
Representative(s)Moncheny, Michel, et al
Cabinet Lavoix
2, Place d'Estienne d'Orves
75441 Paris Cedex 09 / FR
[N/P]
Former [1991/51]Moncheny, Michel, et al
c/o Cabinet Lavoix 2 Place d'Estienne d'Orves
F-75441 Paris Cedex 09 / FR
Former [1988/09]Klein, Daniel Jacques Henri
Compagnie IBM France Département de Propriété Intellectuelle
F-06610 La Gaude / FR
Application number, filing date87110152.314.07.1987
[1988/09]
Priority number, dateUS1986090149228.08.1986         Original published format: US 901492
[1988/09]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0257277
Date:02.03.1988
Language:EN
[1988/09]
Type: A3 Search report 
No.:EP0257277
Date:18.07.1990
Language:EN
[1990/29]
Search report(s)(Supplementary) European search report - dispatched on:EP30.05.1990
ClassificationIPC:H01L21/00, H01L21/263, H01L21/203, H01L21/90, C23C14/34
[1990/26]
CPC:
H01L21/76877 (EP,US)
Former IPC [1990/25]H01L21/00, H01L21/263, H01L21/203, C23C14/34
Former IPC [1988/09]H01L21/00, H01L21/263
Designated contracting statesDE,   FR,   GB,   IT [1988/09]
TitleGerman:Verfahren zur simultanen Herstellung von einer Verbindungsebene und von Durchgangsstifte[1988/09]
English:Method for simultaneously forming a interconnection level and via studs[1988/09]
French:Procédé pour la fabrication simultanée d'un niveau d'interconnection et de pointes traversantes[1988/09]
File destroyed:12.06.1999
Examination procedure16.06.1988Examination requested  [1988/33]
29.08.1991Despatch of a communication from the examining division (Time limit: M06)
10.03.1992Application deemed to be withdrawn, date of legal effect  [1992/37]
13.04.1992Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time  [1992/37]
Fees paidRenewal fee
25.07.1989Renewal fee patent year 03
23.07.1990Renewal fee patent year 04
18.07.1991Renewal fee patent year 05
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Documents cited:Search[Y]US4107726  (SCHILLING HARTMUT);
 [Y]US4111775  (HOLLIS JR BEN R, et al);
 [Y]US4523372  (BALDA RAYMOND J [US], et al);
 [XP]WO8703013  (EASTMAN KODAK CO [US])
 [X]  - PROCEEDINGS OF THE 2nd INTERNATIONAL IEEE VLSI MULTILEVEL INTERCONNECTION CONFERENCE
 [X]  - THIN SOLID FILMS
 [Y]  - PROCEEDINGS OF THE 3rd INTERNATIONAL IEEE VLSI MULTILEVEL INTERCONNECTION CONFERENCE
 [A]  - SOLID STATE TECHNOLOGY
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.