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EP0266873
European procedure
Extract from the Register of European Patents
EP About this file: EP0266873
| EP0266873 - Programmable logic array [Right-click to bookmark this link] | |||
| Former [1988/19] | Testing programmable logic arrays | ||
| [1993/30] | Status | No opposition filed within time limit Status updated on 02.06.1994 Database last updated on 07.10.2024 | Most recent event Tooltip | 02.06.1994 | No opposition filed within time limit | published on 20.07.1994 [1994/29] | Applicant(s) | For all designated states INTERNATIONAL COMPUTERS LIMITED ICL House Putney, London, SW15 1SW / GB | [N/P] |
| Former [1988/19] | For all designated states INTERNATIONAL COMPUTERS LIMITED ICL House Putney, London, SW15 1SW / GB | Inventor(s) | 01 /
Illman, Richard John 66, Deneside Crescent Hazel Grove Stockport SK7 4NU / GB | [1988/19] | Representative(s) | Guyatt, Derek Charles, et al International Computers Limited Intellectual Property Department Cavendish Road Stevenage, Herts, SG1 2DY / GB | [N/P] |
| Former [1994/28] | Guyatt, Derek Charles, et al Intellectual Property Department International Computers Limited Cavendish Road Stevenage, Herts, SG1 2DY / GB | ||
| Former [1988/19] | Guyatt, Derek Charles Intellectual Property Department International Computers Limited Cavendish Road Stevenage, Herts, SG1 2DY / GB | Application number, filing date | 87307945.3 | 09.09.1987 | [1988/19] | Priority number, date | GB19860026516 | 06.11.1986 Original published format: GB 8626516 | [1988/19] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0266873 | Date: | 11.05.1988 | Language: | EN | [1988/19] | Type: | A3 Search report | No.: | EP0266873 | Date: | 06.06.1990 | Language: | EN | [1990/23] | Type: | B1 Patent specification | No.: | EP0266873 | Date: | 28.07.1993 | Language: | EN | [1993/30] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 19.04.1990 | Classification | IPC: | G06F11/26 | [1988/19] | CPC: |
G06F11/2215 (EP,US);
G01R31/318516 (EP,US)
| Designated contracting states | BE, DE, FR, GB, NL [1988/19] | Title | German: | Programmierbare logische Anordnung | [1993/30] | English: | Programmable logic array | [1993/30] | French: | Réseau logique programmable | [1993/30] |
| Former [1988/19] | Prüfung programmierbarer logischer Anordnungen | ||
| Former [1988/19] | Testing programmable logic arrays | ||
| Former [1988/19] | Test de réseaux logiques programmables | Examination procedure | 27.04.1990 | Examination requested [1990/26] | 20.11.1992 | Despatch of communication of intention to grant (Approval: Yes) | 25.01.1993 | Communication of intention to grant the patent | 05.02.1993 | Fee for grant paid | 05.02.1993 | Fee for publishing/printing paid | Opposition(s) | 29.04.1994 | No opposition filed within time limit [1994/29] | Fees paid | Renewal fee | 10.08.1989 | Renewal fee patent year 03 | 16.07.1990 | Renewal fee patent year 04 | 05.08.1991 | Renewal fee patent year 05 | 06.08.1992 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [AD]GB2172726 (INT COMPUTERS LTD) | [A] - IEEE TRANSACTIONS ON COMPUTERS, vol. C-32, no. 11, November 1983, pages 1038-1046, New York, US; K.K. SALUJI et al.: "An easily testable design of programmable logic arrays for multiple faults" | [A] - INT. TEST CONF. 1986 PROCEEDINGS, 8th - 11th September 1986, Testings impact on design & technology, pages 688-695; D.S. HA: "On the design of random pattern testable PLAs" | [A] - IEEE DESIGN & TEST OF COMPUTERS, vol. 2, no. 2, April 1985, pages 37-48, New York, US; R. TREUER et al.: "Implementing a built-in self-test PLA design" | [A] - PROC. OF THE IEEE 1985 CUSTOM INTEGRATED CIRCUITS CONF., 20th - 23rd May 1985, pages 306-310; P. VARMA et al.: "On-chip testing of embedded PLAs" |