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EP0279332
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EP About this file: EP0279332
| EP0279332 - A logic circuit used in standard IC of CMOS logic level [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 11.02.1992 Database last updated on 02.11.2024 | Most recent event Tooltip | 11.02.1992 | Application deemed to be withdrawn | published on 01.04.1992 [1992/14] | Applicant(s) | For all designated states Kabushiki Kaisha Toshiba 72, Horikawa-cho, Saiwai-ku Kawasaki-shi Kanagawa-ken 210-8572 / JP | [N/P] |
| Former [1988/34] | For all designated states KABUSHIKI KAISHA TOSHIBA 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210, Tokyo / JP | Inventor(s) | 01 /
Masuoka, Hideaki Patent Division Kabushiki Kaisha Toshiba 1-1 Shibaura 1-chome Minato-ku Tokyo 105 / JP | [1988/34] | Representative(s) | Henkel & Partner mbB Patentanwaltskanzlei, Rechtsanwaltskanzlei Maximiliansplatz 21 80333 München / DE | [N/P] |
| Former [1988/34] | Henkel, Feiler, Hänzel & Partner Möhlstrasse 37 D-81675 München / DE | Application number, filing date | 88101894.9 | 09.02.1988 | [1988/34] | Priority number, date | JP19870034133 | 17.02.1987 Original published format: JP 3413387 | [1988/34] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0279332 | Date: | 24.08.1988 | Language: | EN | [1988/34] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 04.07.1988 | Classification | IPC: | H03K19/094, H03K19/082, H03K19/01, H03K19/003 | [1988/34] | CPC: |
H03K19/0013 (EP,US);
H03K19/08 (KR);
H03K19/09448 (EP,US)
| Designated contracting states | DE, FR, GB [1988/34] | Title | German: | In Standard-IC's mit CMOS-Logikpegel verwendete Logikschaltung | [1988/34] | English: | A logic circuit used in standard IC of CMOS logic level | [1988/34] | French: | Circuit logique utilisé dans des circuits intégrés standard à niveau de logique CMOS | [1988/34] | File destroyed: | 12.06.1999 | Examination procedure | 04.03.1988 | Examination requested [1988/34] | 02.01.1990 | Despatch of a communication from the examining division (Time limit: M04) | 07.05.1990 | Reply to a communication from the examining division | 07.08.1990 | Despatch of a communication from the examining division (Time limit: M06) | 07.12.1990 | Reply to a communication from the examining division | 07.05.1991 | Despatch of a communication from the examining division (Time limit: M04) | 18.09.1991 | Application deemed to be withdrawn, date of legal effect [1992/14] | 21.10.1991 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time [1992/14] | Fees paid | Renewal fee | 14.02.1990 | Renewal fee patent year 03 | 17.12.1990 | Renewal fee patent year 04 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]JP59205828 ; | [A]EP0145004 (HITACHI LTD [JP]); | [A]US4616146 (LEE SHI-CHUAN [US], et al); | [A]US4638186 (MCLAUGHLIN KEVIN L [US]); | [XP]EP0212004 (TOSHIBA KK [JP]) | [A] - PATENT ABSTRACTS OF JAPAN, vol. 9, no. 69 (E-305)[1792], 29th March 1985; & JP-A-59 205 828 (NIPPON DENKI K.K.) 21-11-1984, & JP59205828 A 00000000 | [A] - EDN ELECTRICAL DESIGN NEWS, vol. 29, no. 8, April 1984, pages 285-290, 292, 294, 296, Boston, US; L. WAKEMAN "High-speed-CMOS-designs address noise and I/O levels" |