-
EP0293923
European procedure
Extract from the Register of European Patents
EP About this file: EP0293923
| EP0293923 - Latch circuit constructed with MOS transistors and shift register using the latch circuits [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 18.06.1994 Database last updated on 03.10.2024 | Most recent event Tooltip | 18.06.1994 | No opposition filed within time limit | published on 10.08.1994 [1994/32] | Applicant(s) | For all designated states Kabushiki Kaisha Toshiba 72, Horikawa-cho, Saiwai-ku Kawasaki-shi Kanagawa-ken 210-8572 / JP | [N/P] |
| Former [1988/49] | For all designated states KABUSHIKI KAISHA TOSHIBA 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210, Tokyo / JP | Inventor(s) | 01 /
Nakagawa, Kaoru c/o Patent Division Kabushiki Kaisha Toshiba 1-1 Shibaura 1-chome Minato-ku Tokyo 105 / JP | 02 /
Nagaba, Katsushi c/o Patent Division Kabushiki Kaisha Toshiba 1-1 Shibaura 1-chome Minato-ku Tokyo 105 / JP | [1989/06] |
| Former [1988/49] | 01 /
Nakagawa, Koaru c/o Patent Division Kabushiki Kaisha Toshiba 1-1 Shibaura 1-chome Minato-ku Tokyo 105 / JP | ||
| 02 /
Nagaba, Katsushi c/o Patent Division Kabushiki Kaisha Toshiba 1-1 Shibaura 1-chome Minato-ku Tokyo 105 / JP | Representative(s) | Henkel & Partner mbB Patentanwaltskanzlei, Rechtsanwaltskanzlei Maximiliansplatz 21 80333 München / DE | [N/P] |
| Former [1988/49] | Henkel, Feiler, Hänzel & Partner Möhlstrasse 37 D-81675 München / DE | Application number, filing date | 88108929.6 | 03.06.1988 | [1988/49] | Priority number, date | JP19870139406 | 03.06.1987 Original published format: JP 13940687 | [1988/49] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0293923 | Date: | 07.12.1988 | Language: | EN | [1988/49] | Type: | A3 Search report | No.: | EP0293923 | Date: | 22.08.1990 | Language: | EN | [1990/34] | Type: | B1 Patent specification | No.: | EP0293923 | Date: | 18.08.1993 | Language: | EN | [1993/33] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 03.07.1990 | Classification | IPC: | G11C19/28, H03K3/356, G11C7/00 | [1990/33] | CPC: |
G11C19/28 (EP,US);
G11C19/00 (KR);
H03K3/356104 (EP,US)
|
| Former IPC [1988/49] | G11C7/00, G11C19/28 | Designated contracting states | DE, FR, GB [1988/49] | Title | German: | Verriegelungsschaltung mit MOS-Transistoren und Schieberegister mit solchen Verriegelungsschaltungen | [1988/49] | English: | Latch circuit constructed with MOS transistors and shift register using the latch circuits | [1988/49] | French: | Circuit de verrouillage réalisé avec des transitors MOS, et registre à décalage utilisant ces circuits de verrouillage | [1988/49] | Examination procedure | 30.06.1988 | Examination requested [1988/49] | 07.09.1992 | Despatch of communication of intention to grant (Approval: Yes) | 07.01.1993 | Communication of intention to grant the patent | 31.03.1993 | Fee for grant paid | 31.03.1993 | Fee for publishing/printing paid | Opposition(s) | 19.05.1994 | No opposition filed within time limit [1994/32] | Fees paid | Renewal fee | 12.06.1990 | Renewal fee patent year 03 | 17.12.1990 | Renewal fee patent year 04 | 09.06.1992 | Renewal fee patent year 05 | 14.06.1993 | Renewal fee patent year 06 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]JP5637890 ; | [A]EP0180193 (TOSHIBA KK [JP]) | [A] - PATENT ABSTRACTS OF JAPAN, vol. 5, no. 92 (P-66)[764], 16th June 1981; & JP-A-56 37 890 (TOKYO SHIBAURA DENKI K.K.) 11-04-1981, & JP5637890 A 00000000 |