EP0290066 - Test method for LCD elements [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 27.01.1994 Database last updated on 31.08.2024 | Most recent event Tooltip | 27.01.1994 | No opposition filed within time limit | published on 16.03.1994 [1994/11] | Applicant(s) | For all designated states Koninklijke Philips Electronics N.V. Groenewoudseweg 1 5621 BA Eindhoven / NL | [N/P] |
Former [1988/45] | For all designated states Philips Electronics N.V. Groenewoudseweg 1 NL-5621 BA Eindhoven / NL | Inventor(s) | 01 /
Hartman, Robert Arnold c/o INT. OCTROOIBUREAU B.V. Prof. Holstlaan 6 NL-5656 AA Eindhoven / NL | 02 /
Peloschek, Hans Peter c/o INT. OCTROOIBUREAU B.V. Prof. Holstlaan 6 NL-5656 AA Eindhoven / NL | [1988/45] | Representative(s) | Raap, Adriaan Yde, et al Philips Intellectual Property & Standards P.O. Box 220 5600 AE Eindhoven / NL | [N/P] |
Former [1988/45] | Raap, Adriaan Yde, et al INTERNATIONAAL OCTROOIBUREAU B.V., Prof. Holstlaan 6 NL-5656 AA Eindhoven / NL | Application number, filing date | 88200707.3 | 13.04.1988 | [1988/45] | Priority number, date | NL19870000933 | 21.04.1987 Original published format: NL 8700933 | [1988/45] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0290066 | Date: | 09.11.1988 | Language: | EN | [1988/45] | Type: | B1 Patent specification | No.: | EP0290066 | Date: | 24.03.1993 | Language: | EN | [1993/12] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 15.09.1988 | Classification | IPC: | G01R31/305, G01R31/308 | [1993/12] | CPC: |
G01R31/305 (EP,US);
H01L22/00 (KR);
G01R31/308 (EP,US);
Y10S345/904 (EP,US)
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Former IPC [1988/45] | G01R31/28 | Designated contracting states | CH, DE, FR, GB, IT, LI, NL, SE [1988/45] | Title | German: | Prüfverfahren für LCD-Elemente | [1988/45] | English: | Test method for LCD elements | [1988/45] | French: | Procédé de test pour circuits LCD | [1988/45] | Examination procedure | 26.04.1989 | Examination requested [1989/27] | 11.11.1991 | Despatch of a communication from the examining division (Time limit: M04) | 11.02.1992 | Reply to a communication from the examining division | 04.05.1992 | Despatch of communication of intention to grant (Approval: Yes) | 15.09.1992 | Communication of intention to grant the patent | 30.09.1992 | Fee for grant paid | 30.09.1992 | Fee for publishing/printing paid | Opposition(s) | 28.12.1993 | No opposition filed within time limit [1994/11] | Fees paid | Renewal fee | 24.04.1990 | Renewal fee patent year 03 | 25.04.1991 | Renewal fee patent year 04 | 29.04.1992 | Renewal fee patent year 05 |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | CH | 24.03.1993 | LI | 24.03.1993 | SE | 24.03.1993 | [1993/46] |
Former [1993/45] | CH | 24.03.1993 | |
LI | 24.03.1993 | Documents cited: | Search | [A]US4172228 (GAUTHIER MICHAEL K [US], et al); | [AD]DE2831787 (SIEMENS AG); | [A]EP0104579 (SIEMENS AG [DE]); | [X]EP0143039 (COMMISSARIAT ENERGIE ATOMIQUE [FR]) | [Y] - SOLID STATE TECHNOLOGY, vol. 27, no. 2, February 1984, pages 135-139, Port Washington, NY, US; D.C. SHAVER: "Electron-beam customization, repair and testing of wafer-scale circuits" |