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Extract from the Register of European Patents

EP About this file: EP0290066

EP0290066 - Test method for LCD elements [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  27.01.1994
Database last updated on 31.08.2024
Most recent event   Tooltip27.01.1994No opposition filed within time limitpublished on 16.03.1994 [1994/11]
Applicant(s)For all designated states
Koninklijke Philips Electronics N.V.
Groenewoudseweg 1
5621 BA Eindhoven / NL
[N/P]
Former [1988/45]For all designated states
Philips Electronics N.V.
Groenewoudseweg 1
NL-5621 BA Eindhoven / NL
Inventor(s)01 / Hartman, Robert Arnold
c/o INT. OCTROOIBUREAU B.V. Prof. Holstlaan 6
NL-5656 AA Eindhoven / NL
02 / Peloschek, Hans Peter
c/o INT. OCTROOIBUREAU B.V. Prof. Holstlaan 6
NL-5656 AA Eindhoven / NL
[1988/45]
Representative(s)Raap, Adriaan Yde, et al
Philips Intellectual Property & Standards P.O. Box 220
5600 AE Eindhoven / NL
[N/P]
Former [1988/45]Raap, Adriaan Yde, et al
INTERNATIONAAL OCTROOIBUREAU B.V., Prof. Holstlaan 6
NL-5656 AA Eindhoven / NL
Application number, filing date88200707.313.04.1988
[1988/45]
Priority number, dateNL1987000093321.04.1987         Original published format: NL 8700933
[1988/45]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP0290066
Date:09.11.1988
Language:EN
[1988/45]
Type: B1 Patent specification 
No.:EP0290066
Date:24.03.1993
Language:EN
[1993/12]
Search report(s)(Supplementary) European search report - dispatched on:EP15.09.1988
ClassificationIPC:G01R31/305, G01R31/308
[1993/12]
CPC:
G01R31/305 (EP,US); H01L22/00 (KR); G01R31/308 (EP,US);
Y10S345/904 (EP,US)
Former IPC [1988/45]G01R31/28
Designated contracting statesCH,   DE,   FR,   GB,   IT,   LI,   NL,   SE [1988/45]
TitleGerman:Prüfverfahren für LCD-Elemente[1988/45]
English:Test method for LCD elements[1988/45]
French:Procédé de test pour circuits LCD[1988/45]
Examination procedure26.04.1989Examination requested  [1989/27]
11.11.1991Despatch of a communication from the examining division (Time limit: M04)
11.02.1992Reply to a communication from the examining division
04.05.1992Despatch of communication of intention to grant (Approval: Yes)
15.09.1992Communication of intention to grant the patent
30.09.1992Fee for grant paid
30.09.1992Fee for publishing/printing paid
Opposition(s)28.12.1993No opposition filed within time limit [1994/11]
Fees paidRenewal fee
24.04.1990Renewal fee patent year 03
25.04.1991Renewal fee patent year 04
29.04.1992Renewal fee patent year 05
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Lapses during opposition  TooltipCH24.03.1993
LI24.03.1993
SE24.03.1993
[1993/46]
Former [1993/45]CH24.03.1993
LI24.03.1993
Documents cited:Search[A]US4172228  (GAUTHIER MICHAEL K [US], et al);
 [AD]DE2831787  (SIEMENS AG);
 [A]EP0104579  (SIEMENS AG [DE]);
 [X]EP0143039  (COMMISSARIAT ENERGIE ATOMIQUE [FR])
 [Y]  - SOLID STATE TECHNOLOGY, vol. 27, no. 2, February 1984, pages 135-139, Port Washington, NY, US; D.C. SHAVER: "Electron-beam customization, repair and testing of wafer-scale circuits"
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.