-
EP0283228
European procedure
- EP About this file
- EP Legal status
- EP Federated register
- EP Event history
- EP Citations
- EP Patent family
- EP All documents
Extract from the Register of European Patents
EP About this file: EP0283228
| EP0283228 - Dynamic type decoder circuit [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 26.10.1993 Database last updated on 03.10.2024 | Most recent event Tooltip | 26.10.1993 | Application deemed to be withdrawn | published on 15.12.1993 [1993/50] | Applicant(s) | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi Kanagawa 211 / JP | [N/P] |
| Former [1988/38] | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 / JP | Inventor(s) | 01 /
Okano, Yoshiaki Yamada Bldg, 101 7-5-9, Yanaka Taito-ku Tokyo 110 / JP | [1988/38] | Representative(s) | Billington, Lawrence Emlyn, et al Haseltine Lake LLP Lincoln House, 5th Floor 300 High Holborn London WC1V 7JH / GB | [N/P] |
| Former [1988/38] | Billington, Lawrence Emlyn, et al HASELTINE LAKE & CO Hazlitt House 28 Southampton Buildings Chancery Lane London WC2A 1AT / GB | Application number, filing date | 88302200.6 | 14.03.1988 | [1988/38] | Priority number, date | JP19870061123 | 18.03.1987 Original published format: JP 6112387 | [1988/38] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0283228 | Date: | 21.09.1988 | Language: | EN | [1988/38] | Type: | A3 Search report | No.: | EP0283228 | Date: | 27.12.1990 | Language: | EN | [1990/52] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 05.11.1990 | Classification | IPC: | G11C8/00 | [1988/38] | CPC: |
G11C8/10 (EP,US);
G11C7/00 (KR);
G11C8/06 (EP,US)
| Designated contracting states | DE, FR, GB [1988/38] | Title | German: | Dekodierer des dynamischen Typs | [1988/38] | English: | Dynamic type decoder circuit | [1988/38] | French: | Circuit décodeur de type dynamique | [1988/38] | File destroyed: | 12.06.1999 | Examination procedure | 28.12.1990 | Examination requested [1991/10] | 02.04.1992 | Despatch of a communication from the examining division (Time limit: M06) | 13.10.1992 | Application deemed to be withdrawn, date of legal effect [1993/50] | 11.11.1992 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time [1993/50] | Fees paid | Renewal fee | 07.03.1990 | Renewal fee patent year 03 | 07.03.1991 | Renewal fee patent year 04 | 04.03.1992 | Renewal fee patent year 05 | Penalty fee | Additional fee for renewal fee | 31.03.1993 | 06 M06 Not yet paid |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]JP58182184 ; | [X]EP0017688 (MOTOROLA INC [US]) | [X] - PATENT ABSTRACTS OF JAPAN, vol. 8, no. 27 (P-252)[1464], 4th February 1984; & JP-A-58 182 184 (FUJITSU) 25-10-1983, & JP58182184 A 00000000 | [A] - N. WESTE et al.: "Principles of CMOS VLSI Design", 1985, pages 8-16,160-168, Addison Wesley, Reading, US |