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EP0319213
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EP About this file: EP0319213
| EP0319213 - Method for fabricating semiconductor devices which include metal-containing material regions [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 27.06.1997 Database last updated on 25.09.2024 | Most recent event Tooltip | 05.10.2005 | Change: Appeal number | Applicant(s) | For all designated states AT&T Corp. 32 Avenue of the Americas New York, NY 10013-2412 / US | [1989/23] | Inventor(s) | 01 /
Liu, Ruichen 4 Northridge Way Warren New Jersey 07060 / US | 02 /
Lynch, William Thomas 72 Passaic Avenue Summit New Jersey 07901 / US | 03 /
Williams, David Slate 9 Beechwood Drive Convent Station New Jersey 07961 / US | [1989/23] | Representative(s) | Watts, Christopher Malcolm Kelway, et al Lucent Technologies (UK) Ltd, 5 Mornington Road Woodford Green Essex IG8 OTU / GB | [N/P] |
| Former [1989/23] | Watts, Christopher Malcolm Kelway, Dr., et al AT&T (UK) LTD. AT&T Intellectual Property Division 5 Mornington Road Woodford Green Essex IG8 OTU / GB | Application number, filing date | 88311213.8 | 25.11.1988 | [1989/23] | Priority number, date | US19870128742 | 04.12.1987 Original published format: US 128742 | [1989/23] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0319213 | Date: | 07.06.1989 | Language: | EN | [1989/23] | Type: | A3 Search report | No.: | EP0319213 | Date: | 06.12.1989 | Language: | EN | [1989/49] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 17.10.1989 | Classification | IPC: | H01L21/285, H01L21/225, H01L21/28, H01L21/82 | [1989/23] | CPC: |
H01L29/66575 (EP,US);
H01L21/18 (KR);
H01L21/2257 (EP,US);
H01L21/823814 (EP,US);
H01L27/0928 (EP,US);
H01L2924/0002 (EP,US);
Y10S148/019 (EP,US)
(-)
| C-Set: |
H01L2924/0002, H01L2924/00 (EP,US)
| Designated contracting states | DE, ES, FR, GB, NL [1989/23] | Title | German: | Verfahren zur Herstellung von Halbleiteranordnungen, umfassend Metall enthaltende Materialgebiete | [1989/23] | English: | Method for fabricating semiconductor devices which include metal-containing material regions | [1989/23] | French: | Méthode de fabrication de dispositifs semi-conducteurs comprenant des régions de matériau contenant du métal | [1989/23] | Examination procedure | 15.05.1990 | Examination requested [1990/29] | 15.04.1992 | Despatch of a communication from the examining division (Time limit: M06) | 19.10.1992 | Reply to a communication from the examining division | 04.11.1992 | Despatch of a communication from the examining division (Time limit: M04) | 08.03.1993 | Reply to a communication from the examining division | 17.06.1993 | Despatch of communication that the application is refused, reason: substantive examination {1} | 01.03.1997 | Application deemed to be withdrawn, date of legal effect [1997/33] | 24.03.1997 | Despatch of communication that the application is deemed to be withdrawn, reason: A.110(2) in appeal [1997/33] | Appeal following examination | 04.08.1993 | Appeal received No. T0934/93 | 19.10.1993 | Statement of grounds filed | 11.10.1996 | Invitation to file observations in an appeal (Time limit: M04) [1996/41] | 03.04.1997 | Result of appeal procedure: the application was deemed to be withdrawn | Fees paid | Renewal fee | 16.11.1990 | Renewal fee patent year 03 | 21.11.1991 | Renewal fee patent year 04 | 16.11.1992 | Renewal fee patent year 05 | 09.11.1993 | Renewal fee patent year 06 | 16.11.1994 | Renewal fee patent year 07 | 17.11.1995 | Renewal fee patent year 08 | 18.11.1996 | Renewal fee patent year 09 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X] - International Electron Devices Meeting, Los Angeles, 7th-10th December 1986, pages 58-61, IEEE, New YorkUS; R. LIU et al.: "Mechanisms for process-induced leakage in shallow silicided junctions" | [X] - IEEE Transactions on Electron Devices, Vol. ED-34, No. 3, March 1987, pages 575-580, IEEE, New York, NYUS; Y. TAUR et al.: "Source-drain contact resistance in CMOS with self-aligned TiSi2" | [AD] - International Electron Devices Meeting, Washington, DC, 1st-4th December 1985, pages 407-410, IEEE, New YorkUS; F.C. SHONE et al.: "Formation of 0.1 mum N+/P and P+/N junctions by doped silicide technology". | [AD] - 1986 Symposium on VLSI Technology; Digest of Technical Papers, San Diego, 28th-30th May 1986pages 49-50; N. KOBAYASHI et al.: "Comparison of TiSi2 and WSi2 silicided shallow junctions for sub-micron CMOSs" | [A] - IBM Journal of Research & Development, Vol. 31, No. 6, November 1987, pages 627-633, New YorkUS; Y. TAUR et al.: "Study of contact and shallow junction characteristics in submicron CMOS with self-aligned titanium silicide" | [A] - Extended Abstracts, Vol. 87-1, No. 1, Spring 1987, pages 216-217, Abstract No. 156, Philadelphia, PAUS; B. DAVARI et al.: "Very shallow junctions for submicron CMOS technology using implanted Ti for silidation" | [A] - Japanese Journal of Applied Physics - 17th Conference on Solid State Devices and Materials, 25th-27th August 1985, pages 325-328, TokyoJP; N. NATSUAKI et al.: "Refractory-metal-silicide contact formation by rapid thermal annealing" | [A] - IEEE Transactions on Electron Devices, Vol. ED-33, No. 2, February 1986, pages 260-269, IEEE, New YorkUS; M. HORIUCHI et al.: "Solid-II: High-voltage high-gain kilo-Angstrom-channel-length CMOSFET's using silicide with self-aligned utrashallow (3S) junction" |