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EP0346876
European procedure
Extract from the Register of European Patents
EP About this file: EP0346876
| EP0346876 - Semiconductor integrated circuit having a CMOS inverter [Right-click to bookmark this link] | |||
| Former [1989/51] | Semiconductor integrated circuit having a cmos inverter | ||
| [1994/37] | Status | No opposition filed within time limit Status updated on 15.07.1995 Database last updated on 14.03.2026 | Most recent event Tooltip | 15.07.1995 | No opposition filed within time limit | published on 06.09.1995 [1995/36] | Applicant(s) | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi Kanagawa 211 / JP | For all designated states FUJITSU VLSI LIMITED 1844-2, Kozoji-cho 2-chome Kasugai-shi Aichi 487 / JP | [N/P] |
| Former [1989/51] | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 / JP | ||
| For all designated states FUJITSU VLSI LIMITED 1844-2, Kozoji-cho 2-chome Kasugai-shi Aichi 487 / JP | Inventor(s) | 01 /
Shizu, Harumi 1-130-1-102, Mizuhodori Kasugai-shi Aichi, 486 / JP | [1989/51] | Representative(s) | Schmidt-Evers, Jürgen, et al Mitscherlich PartmbB Patent- und Rechtsanwälte Postfach 33 06 09 80066 München / DE | [N/P] |
| Former [1989/51] | Schmidt-Evers, Jürgen, Dipl.-Ing., et al Patentanwälte Mitscherlich & Partner Postfach 33 06 09 D-80066 München / DE | Application number, filing date | 89110814.4 | 14.06.1989 | [1989/51] | Priority number, date | JP19880150848 | 17.06.1988 Original published format: JP 15084888 | [1989/51] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0346876 | Date: | 20.12.1989 | Language: | EN | [1989/51] | Type: | B1 Patent specification | No.: | EP0346876 | Date: | 14.09.1994 | Language: | EN | [1994/37] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 16.10.1989 | Classification | IPC: | H03K19/003 | [1989/51] | CPC: |
H03K19/00361 (EP,US);
H03K19/003 (KR)
| Designated contracting states | DE, FR, GB [1989/51] | Title | German: | Integrierte Halbleiterschaltung mit einem CMOS-Inverter | [1989/51] | English: | Semiconductor integrated circuit having a CMOS inverter | [1994/37] | French: | Circuit intégré à semi-conducteurs ayant un inverseur CMOS | [1989/51] |
| Former [1989/51] | Semiconductor integrated circuit having a cmos inverter | Examination procedure | 19.06.1990 | Examination requested [1990/33] | 30.04.1992 | Despatch of a communication from the examining division (Time limit: M06) | 03.11.1992 | Reply to a communication from the examining division | 08.12.1992 | Despatch of a communication from the examining division (Time limit: M04) | 08.04.1993 | Reply to a communication from the examining division | 11.05.1993 | Despatch of a communication from the examining division (Time limit: M04) | 15.09.1993 | Reply to a communication from the examining division | 08.10.1993 | Despatch of communication of intention to grant (Approval: Yes) | 14.02.1994 | Communication of intention to grant the patent | 16.05.1994 | Fee for grant paid | 16.05.1994 | Fee for publishing/printing paid | Opposition(s) | 15.06.1995 | No opposition filed within time limit [1995/36] | Fees paid | Renewal fee | 28.06.1991 | Renewal fee patent year 03 | 30.06.1992 | Renewal fee patent year 04 | 30.06.1993 | Renewal fee patent year 05 | 29.06.1994 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X] PATENT ABSTRACTS OF JAPAN | Examination | JP61292412 | PATENT ABSTRACTS OF JAPAN, vol.11, no.154 (E-508)(2601) 19 May 1987 & JP-A-61292412 |