-
EP0356986
European procedure
Extract from the Register of European Patents
EP About this file: EP0356986
| EP0356986 - Buffer circuit for logic level conversion [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 16.02.1995 Database last updated on 11.09.2024 | Most recent event Tooltip | 26.07.1995 | Lapse of the patent in a contracting state New state(s): GB | published on 13.09.1995 [1995/37] | Applicant(s) | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi Kanagawa 211 / JP | [N/P] |
| Former [1990/10] | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 / JP | Inventor(s) | 01 /
Kajii, Kiyoshi 1964-2-201, Nurumizu Atsugi-shi Kanagawa, 243 / JP | [1990/10] | Representative(s) | Schmidt-Evers, Jürgen, et al Mitscherlich PartmbB Patent- und Rechtsanwälte Postfach 33 06 09 80066 München / DE | [N/P] |
| Former [1990/10] | Schmidt-Evers, Jürgen, Dipl.-Ing., et al Patentanwälte Mitscherlich & Partner Postfach 33 06 09 D-80066 München / DE | Application number, filing date | 89115900.6 | 29.08.1989 | [1990/10] | Priority number, date | JP19880216732 | 30.08.1988 Original published format: JP 21673288 | [1990/10] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0356986 | Date: | 07.03.1990 | Language: | EN | [1990/10] | Type: | A3 Search report | No.: | EP0356986 | Date: | 19.09.1990 | Language: | EN | [1990/38] | Type: | B1 Patent specification | No.: | EP0356986 | Date: | 13.04.1994 | Language: | EN | [1994/15] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 02.08.1990 | Classification | IPC: | H03K19/094 | [1990/10] | CPC: |
H03K19/018535 (EP,US);
H03K19/00 (KR);
H03K19/00384 (EP,US);
H03K19/01707 (EP,US)
| Designated contracting states | DE, FR, GB [1990/10] | Title | German: | Pufferschaltung für logische Pegelumsetzung | [1990/10] | English: | Buffer circuit for logic level conversion | [1990/10] | French: | Circuit tampon pour la conversion de niveaux logiques | [1990/10] | Examination procedure | 15.11.1990 | Examination requested [1991/02] | 28.07.1992 | Despatch of a communication from the examining division (Time limit: M04) | 30.11.1992 | Reply to a communication from the examining division | 10.12.1992 | Despatch of a communication from the examining division (Time limit: M05) | 07.05.1993 | Reply to a communication from the examining division | 05.07.1993 | Despatch of communication of intention to grant (Approval: Yes) | 07.10.1993 | Communication of intention to grant the patent | 16.11.1993 | Fee for grant paid | 16.11.1993 | Fee for publishing/printing paid | Opposition(s) | 14.01.1995 | No opposition filed within time limit [1995/14] | Fees paid | Renewal fee | 30.08.1991 | Renewal fee patent year 03 | 31.08.1992 | Renewal fee patent year 04 | 30.08.1993 | Renewal fee patent year 05 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | DE | 13.04.1994 | GB | 29.08.1994 | [1995/37] |
| Former [1995/03] | DE | 13.04.1994 | Documents cited: | Search | [A]JP5550743 ; | [AP]US4767951 (CORNISH ELDON C [US], et al) | [A] - PROCEEDINGS OF THE IEEE 1986 CUSTOM INTEGRATED CIRCUITS CONFERENCE, Rochester, New York, 12th - 15th May 1986, pages 508-512, IEEE, New York, US; D.P. LAUDE: "An ECL compatible GaAs 504 4-input nor gate array" | [A] - PATENT ABSTRACTS OF JAPAN, vol. 4, no. 83 (E-15)[565], 14th June 1980, page 129 E 15; & JP-A-55 50 743 (FUJITSU K.K.) 12-04-1980, & JP5550743 A 00000000 | Examination | EP0154337 | EP0292713 | EP0313810 |