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Extract from the Register of European Patents

EP About this file: EP0329400

EP0329400 - Semiconductor thin film and process for fabricating the same [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  23.07.1994
Database last updated on 05.10.2024
Most recent event   Tooltip23.07.1994No opposition filed within time limitpublished on 14.09.1994 [1994/37]
Applicant(s)For all designated states
Oki Electric Industry Company, Limited
7-12, Toranomon 1-chome Minato-ku
Tokyo 105 / JP
[N/P]
Former [1989/34]For all designated states
Oki Electric Industry Company, Limited
7-12, Toranomon 1-chome Minato-ku
Tokyo 105 / JP
Inventor(s)01 / Horikawa, Hideaki
7-12, Toranomon 1-chome
Minatoku Tokyo / JP
02 / Akiyama, Masahiro
7-12, Toranomon 1-chome
Minatoku Tokyo / JP
[1989/34]
Representative(s)Boydell, John Christopher, et al
Stevens, Hewlett & Perkins Halton House 20/23 Holborn
London EC1N 2JD / GB
[N/P]
Former [1989/34]Boydell, John Christopher, et al
Stevens, Hewlett & Perkins 1 Serjeants' Inn Fleet Street
London EC4Y 1LL / GB
Application number, filing date89301423.315.02.1989
[1989/34]
Priority number, dateJP1988003187816.02.1988         Original published format: JP 3187888
[1989/34]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0329400
Date:23.08.1989
Language:EN
[1989/34]
Type: A3 Search report 
No.:EP0329400
Date:16.08.1990
Language:EN
[1990/33]
Type: B1 Patent specification 
No.:EP0329400
Date:22.09.1993
Language:EN
[1993/38]
Search report(s)(Supplementary) European search report - dispatched on:EP26.06.1990
ClassificationIPC:H01L31/18, H01L33/00, H01L21/205
[1989/34]
CPC:
H01L33/0066 (EP,US); H01L21/02381 (EP,US); H01L21/02461 (EP,US);
H01L21/02463 (EP,US); H01L21/02502 (EP,US); H01L21/02513 (EP,US);
H01L21/02543 (EP,US); H01L21/0262 (EP,US); H01L31/1852 (EP,US);
Y02E10/544 (US); Y10S148/025 (EP,US); Y10S148/072 (EP,US);
Y10S148/097 (EP,US); Y10S438/938 (EP,US) (-)
Designated contracting statesDE,   FR,   GB,   NL [1989/34]
TitleGerman:Halbleiter-Dünnschicht und Herstellungsverfahren[1989/34]
English:Semiconductor thin film and process for fabricating the same[1989/34]
French:Couche mince semi-conductrice et procédé pour sa formation[1989/34]
Examination procedure23.01.1991Examination requested  [1991/12]
18.08.1992Despatch of a communication from the examining division (Time limit: M04)
23.11.1992Reply to a communication from the examining division
08.02.1993Despatch of communication of intention to grant (Approval: Yes)
24.03.1993Communication of intention to grant the patent
02.04.1993Fee for grant paid
02.04.1993Fee for publishing/printing paid
Opposition(s)23.06.1994No opposition filed within time limit [1994/37]
Fees paidRenewal fee
08.12.1990Renewal fee patent year 03
23.01.1992Renewal fee patent year 04
23.01.1993Renewal fee patent year 05
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Documents cited:Search[X]US4561916  (AKIYAMA MASAHIRO [JP], et al);
 [XP]EP0291346  (SHARP KK [JP])
 [A]  - SOLID STATE TECHNOLOGY. vol. 30, no. 11, November 1987, WASHINGTON US pages 91 - 97; K.KAMINISHI: "GaAs ON Si TECHNOLOGY"
 [A]  - APPLIED PHYSICS LETTERS. vol. 52, no. 3, 18 January 1988, NEW YORK US pages 209 - 211; M.Razeghi et al.: "High-quality GaInAsP/InP heterostructures grown by low-pressure metalorganic chemical vapor deposition on silicon substrates"
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.