EP0380861 - Improved data consistency between cache memories and the main memory in a multi-processor computer system [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 29.10.1999 Database last updated on 02.09.2024 | Most recent event Tooltip | 28.12.2002 | Lapse of the patent in a contracting state New state(s): NL | published on 12.02.2003 [2003/07] | Applicant(s) | For all designated states DIGITAL EQUIPMENT CORPORATION 111 Powdermill Road Maynard Massachusetts 01754-1418 / US | [N/P] |
Former [1990/32] | For all designated states DIGITAL EQUIPMENT CORPORATION 111 Powdermill Road Maynard Massachusetts 01754-1418 / US | Inventor(s) | 01 /
Webb, David A., Jr. 163 Highland Street Berlin Massachusetts 01503 / US | 02 /
Flynn, Michael E. 3 Westview Street Grafton Massachusetts 01519 / US | 03 /
Hetherington, Ricky C. 177 Indian Meadows Northboro Massachusetts 01749 / US | 04 /
Fossum, Tryggve P.O. Box 96 Northboro Massachusetts 01532 / US | 05 /
Arnold, Scott 55 Dodge Road Sutton Massachusetts 01527 / US | 06 /
De La Hunt, Stephen J. P.O. Box 165 Harvard Massachusetts 01451 / US | [1990/32] | Representative(s) | Rees, David Christopher, et al Kilburn & Strode LLP 20 Red Lion Street London WC1R 4PJ / GB | [N/P] |
Former [1990/32] | Rees, David Christopher, et al Kilburn & Strode 30 John Street London WC1N 2DD / GB | Application number, filing date | 89309861.6 | 28.09.1989 | [1990/32] | Priority number, date | US19890306776 | 03.02.1989 Original published format: US 306776 | [1990/32] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0380861 | Date: | 08.08.1990 | Language: | EN | [1990/32] | Type: | A3 Search report | No.: | EP0380861 | Date: | 12.06.1991 | Language: | EN | [1991/24] | Type: | B1 Patent specification | No.: | EP0380861 | Date: | 23.12.1998 | Language: | EN | [1998/52] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 24.04.1991 | Classification | IPC: | G06F12/08 | [1990/32] | CPC: |
G06F12/0822 (EP)
| Designated contracting states | AT, BE, CH, DE, ES, FR, GB, GR, IT, LI, LU, NL, SE [1990/32] | Title | German: | Datenübereinstimmung zwischen Cache-Speichern und dem Hauptspeicher in einem Multiprozessorsystem | [1990/32] | English: | Improved data consistency between cache memories and the main memory in a multi-processor computer system | [1990/32] | French: | Consistance des données entre les anté-mémoires et la mémoire principale dans un système multiprocesseur | [1990/32] | Examination procedure | 05.10.1989 | Examination requested [1990/32] | 11.07.1994 | Despatch of a communication from the examining division (Time limit: M06) | 16.01.1995 | Reply to a communication from the examining division | 19.02.1996 | Despatch of a communication from the examining division (Time limit: M06) | 17.07.1996 | Reply to a communication from the examining division | 28.04.1997 | Despatch of a communication from the examining division (Time limit: M04) | 22.08.1997 | Reply to a communication from the examining division | 02.03.1998 | Despatch of communication of intention to grant (Approval: Yes) | 26.06.1998 | Communication of intention to grant the patent | 12.08.1998 | Fee for grant paid | 12.08.1998 | Fee for publishing/printing paid | Opposition(s) | 24.09.1999 | No opposition filed within time limit [1999/50] | Fees paid | Renewal fee | 09.09.1991 | Renewal fee patent year 03 | 16.10.1992 | Renewal fee patent year 04 | 16.09.1993 | Renewal fee patent year 05 | 25.08.1994 | Renewal fee patent year 06 | 18.08.1995 | Renewal fee patent year 07 | 19.08.1996 | Renewal fee patent year 08 | 22.08.1997 | Renewal fee patent year 09 | 26.08.1998 | Renewal fee patent year 10 | Penalty fee | Additional fee for renewal fee | 30.09.1992 | 04   M06   Fee paid on   16.10.1992 |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | AT | 23.12.1998 | BE | 23.12.1998 | CH | 23.12.1998 | ES | 23.12.1998 | GR | 23.12.1998 | LI | 23.12.1998 | NL | 23.12.1998 | SE | 23.03.1999 | [2003/07] |
Former [2002/24] | AT | 23.12.1998 | |
BE | 23.12.1998 | ||
CH | 23.12.1998 | ||
ES | 23.12.1998 | ||
GR | 23.12.1998 | ||
LI | 23.12.1998 | ||
SE | 23.03.1999 | ||
Former [2001/23] | AT | 23.12.1998 | |
BE | 23.12.1998 | ||
CH | 23.12.1998 | ||
GR | 23.12.1998 | ||
LI | 23.12.1998 | ||
SE | 23.03.1999 | ||
Former [2000/52] | AT | 23.12.1998 | |
BE | 23.12.1998 | ||
CH | 23.12.1998 | ||
LI | 23.12.1998 | ||
Former [2000/50] | AT | 23.12.1998 | |
BE | 23.12.1998 | ||
CH | 29.03.1999 | ||
LI | 29.03.1999 | ||
Former [1999/34] | AT | 23.12.1998 | |
BE | 23.12.1998 | ||
Former [1999/32] | BE | 23.12.1998 | Documents cited: | Search | [X]EP0095598 (IBM [US]) | [X] - PROCEEDINGS OF THE NATIONAL COMPUTER CONFERENCE, New York, 7th - 10th June 1976, vol. 45, pages 749-753, AFIPS, Montvale, US; C.K. TANG: "Cache system design in the tightly coupled multiprocessor system" | [Y] - ACM TRANSACTIONS ON COMPUTER SYSTEMS, vol. 4, no. 4, November 1986, pages 273-298; J. ARCHIBALD et al.: "Cache coherence protocols: Evaluation using a multiprocessor simulation model" |