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Extract from the Register of European Patents

EP About this file: EP0410464

EP0410464 - Semiconductor memory device having diagnostic circuit for memory cells [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  29.07.1995
Database last updated on 02.11.2024
Most recent event   Tooltip29.07.1995No opposition filed within time limitpublished on 20.09.1995 [1995/38]
Applicant(s)For all designated states
NEC Corporation
7-1, Shiba 5-chome Minato-ku
Tokyo 108-8001 / JP
[N/P]
Former [1991/05]For all designated states
NEC CORPORATION
7-1, Shiba 5-chome Minato-ku
Tokyo / JP
Inventor(s)01 / Sugibayashi, Tadahiko, C/o NEC Corporation
7-1 Shiba 5-chome, Minato-ku
Tokyo / JP
[1991/05]
Representative(s)Glawe, Delfs, Moll
Partnerschaft mbB von
Patent- und Rechtsanwälten
Postfach 26 01 62
80058 München / DE
[N/P]
Former [1991/05]Glawe, Delfs, Moll & Partner
Patentanwälte Postfach 26 01 62
D-80058 München / DE
Application number, filing date90114389.126.07.1990
[1991/05]
Priority number, dateJP1989019545827.07.1989         Original published format: JP 19545889
[1991/05]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0410464
Date:30.01.1991
Language:EN
[1991/05]
Type: A3 Search report 
No.:EP0410464
Date:02.01.1992
Language:EN
[1992/01]
Type: B1 Patent specification 
No.:EP0410464
Date:28.09.1994
Language:EN
[1994/39]
Search report(s)(Supplementary) European search report - dispatched on:EP12.11.1991
ClassificationIPC:G11C29/00, G11C11/409, G01R19/165
[1994/39]
CPC:
G11C29/34 (EP); G11C29/50 (EP); G11C11/401 (EP);
G11C2029/5004 (EP)
Former IPC [1991/05]G11C29/00
Designated contracting statesDE,   FR,   GB [1991/05]
TitleGerman:Halbleiterspeichergerät mit Diagnoseschaltung für Speicherzellen[1991/05]
English:Semiconductor memory device having diagnostic circuit for memory cells[1991/05]
French:Dispositif de mémoire à semiconducteur comportant un circuit de diagnostic pour cellules de mémoire[1991/05]
Examination procedure26.07.1990Examination requested  [1991/05]
07.01.1994Despatch of communication of intention to grant (Approval: Yes)
25.02.1994Communication of intention to grant the patent
27.05.1994Fee for grant paid
27.05.1994Fee for publishing/printing paid
Opposition(s)29.06.1995No opposition filed within time limit [1995/38]
Fees paidRenewal fee
20.07.1992Renewal fee patent year 03
16.07.1993Renewal fee patent year 04
20.07.1994Renewal fee patent year 05
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Documents cited:Search[A]US4393475
 [A]  - JEE JOURNAL OF ELECTRONIC ENGINEERING vol. 26, no. 268, April 1989, TOKYO, JAPAN pages 71 - 74; TOSHIO TAKESHIMA ET AL: 'A 55nsec 16Mbit DRAM DEVELPOED BY NEC HAS A BUILT IN SELF-TEST FUNCTION'
 [A]  - IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT vol. 38, no. 3, June 1989, NEW YORK, USA pages 773 - 778; M. JACOMINO ET AL.: 'FAULT DETECTION IN CMOS CIRCUITS BY CONSUMPTION MEASURENENT'
 [A]  - 1986 INTERNATIONAL TEST CONFERENCE PROCEEDINGS 8 August 1986, WASHINGTON, USA pages 140 - 144; G.G. FREEMAN ET AL.: 'TWO CMOS METASTABILITY SENSORS'
 [A]  - ICCD 88 3 October 1988, NEW YORK, USA pages 454 - 457; D.B.I. FELTHAM ET AL: 'CURRENT SENSING FOR BUILT-IN TESTING OF CMOS CIRCUITS'
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.