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EP0411504
European procedure
Extract from the Register of European Patents
EP About this file: EP0411504
| EP0411504 - Digital signal processing circuit [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 16.04.1999 Database last updated on 14.03.2026 | Most recent event Tooltip | 16.04.1999 | No opposition filed within time limit | published on 02.06.1999 [1999/22] | Applicant(s) | For all designated states Sony Corporation 7-35 Kitashinagawa 6-chome Shinagawa-ku Tokyo 141 / JP | [N/P] |
| Former [1991/06] | For all designated states SONY CORPORATION 7-35 Kitashinagawa 6-chome Shinagawa-ku Tokyo 141 / JP | Inventor(s) | 01 /
Fujita, Tadao C/o Sony Corporation, 7-35 Kitashinagawa 6-chome Shinagawa-ku, Tokyo / JP | 02 /
Inaba, Yoshiaki C/o Sony Corporation, 7-35 Kitashinagawa 6-chome Shinagawa-ku, Tokyo / JP | 03 /
Takayama, Jun C/o Sony Corporation, 7-35 Kitashinagawa 6-chome Shinagawa-ku, Tokyo / JP | [1991/06] | Representative(s) | Schmidt-Evers, Jürgen, et al Mitscherlich PartmbB Patent- und Rechtsanwälte Postfach 33 06 09 80066 München / DE | [N/P] |
| Former [1993/19] | Schmidt-Evers, Jürgen, Dipl.-Ing., et al Patentanwälte Mitscherlich & Partner Postfach 33 06 09 D-80066 München / DE | ||
| Former [1991/06] | Schmidt-Evers, Jürgen, Dipl.-Ing. Patentanwälte Mitscherlich & Partner, Sonnenstrasse 33, Postfach 33 06 09 D-80066 München / DE | Application number, filing date | 90114488.1 | 27.07.1990 | [1991/06] | Priority number, date | JP19890197593 | 29.07.1989 Original published format: JP 19759389 | [1991/06] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0411504 | Date: | 06.02.1991 | Language: | EN | [1991/06] | Type: | A3 Search report | No.: | EP0411504 | Date: | 03.02.1993 | Language: | EN | [1993/05] | Type: | B1 Patent specification | No.: | EP0411504 | Date: | 10.06.1998 | Language: | EN | [1998/24] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 14.12.1992 | Classification | IPC: | G06F7/72, G06F11/00, H03M7/18, G06F11/14, G06F11/10, G06F7/48 | [1993/05] | CPC: |
G06F11/104 (EP,US);
G06F11/1497 (EP,US);
G06F7/72 (KR);
G06F7/729 (EP,US);
H03M7/18 (EP,US)
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| Former IPC [1991/06] | G06F7/72, G06F11/00, H03M7/18 | Designated contracting states | DE, FR, GB [1991/06] | Title | German: | Digitale Signalverarbeitungsschaltung | [1991/06] | English: | Digital signal processing circuit | [1991/06] | French: | Circuit de traitement numérique de signaux | [1991/06] | Examination procedure | 06.07.1993 | Examination requested [1993/35] | 24.10.1995 | Despatch of a communication from the examining division (Time limit: M06) | 19.04.1996 | Reply to a communication from the examining division | 11.09.1996 | Despatch of a communication from the examining division (Time limit: M06) | 04.03.1997 | Reply to a communication from the examining division | 18.08.1997 | Despatch of communication of intention to grant (Approval: Yes) | 05.12.1997 | Communication of intention to grant the patent | 13.02.1998 | Fee for grant paid | 13.02.1998 | Fee for publishing/printing paid | Opposition(s) | 11.03.1999 | No opposition filed within time limit [1999/22] | Fees paid | Renewal fee | 29.07.1992 | Renewal fee patent year 03 | 29.07.1993 | Renewal fee patent year 04 | 07.07.1994 | Renewal fee patent year 05 | 11.07.1995 | Renewal fee patent year 06 | 11.07.1996 | Renewal fee patent year 07 | 14.07.1997 | Renewal fee patent year 08 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A] SU1166116 | [A] JPH0199325 | [A] JPH01126829 | [A] JPS56158525 | [A] IEEE TRANSACTIONS ON COMPUTERS, vol. C-32, no. 4, April 1983, pages 388-396, IEEE; W. KENNETH JENKINS: "The design of error checkers for self-checking residue number arithmetic" [A] | [A] ICASSP 88, V & E, VLSI SPECTRAL ESTIMATION, vol. 4, New York, US, 11th - 14th April 1988, pages 2076-2079, IEEE; M.A. BAYOUMI: "Reliable modulo systolic arrays for DSP algorithms" [A] | [A] SOVIET INVENTIONS ILLUSTRATED, Derwent Publications, Week 8606, T01, 11th February 1986; & SU-A-1 166 116 (AS KAZA MATH MECH) 07-07-1985 [A] | [A] PATENT ABSTRACTS OF JAPAN vol. 013, no. 338 (E - 795) 18 April 1989 (1989-04-18) [A] | [A] PATENT ABSTRACTS OF JAPAN vol. 013, no. 374 (E - 808) 18 May 1989 (1989-05-18) [A] | [A] IEEE TRANSACTIONS ON COMPUTERS, vol. C-23, no. 9, September 1974, pages 915-924; F. BARSI et al.: "Error detection and correction by product codes in residue number systems" [A] | [A] PATENT ABSTRACTS OF JAPAN vol. 006, no. 042 (E - 98) 16 March 1982 (1982-03-16) [A] |