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EP0423826
European procedure
Extract from the Register of European Patents
EP About this file: EP0423826
| EP0423826 - MOS-type integrated circuit [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 23.05.1997 Database last updated on 13.07.2024 | Most recent event Tooltip | 23.05.1997 | No opposition filed within time limit | published on 09.07.1997 [1997/28] | Applicant(s) | For all designated states Kabushiki Kaisha Toshiba 72, Horikawa-cho, Saiwai-ku Kawasaki-shi Kanagawa-ken 210-8572 / JP | [N/P] |
| Former [1991/17] | For all designated states KABUSHIKI KAISHA TOSHIBA 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210, Tokyo / JP | Inventor(s) | 01 /
Shirai, Koji, c/o Intellectual Property Division Kabushiki Kaisha Toshiba, 1-1 Shibaura 1-chome Minato-ku, Tokyo 105 / JP | [1991/17] | Representative(s) | Lehn, Werner, et al Hoffmann Eitle, Patent- und Rechtsanwälte, Postfach 81 04 20 81904 München / DE | [N/P] |
| Former [1991/17] | Lehn, Werner, Dipl.-Ing., et al Hoffmann, Eitle & Partner, Patentanwälte, Postfach 81 04 20 D-81904 München / DE | Application number, filing date | 90120127.7 | 19.10.1990 | [1991/17] | Priority number, date | JP19890272074 | 19.10.1989 Original published format: JP 27207489 | [1991/17] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0423826 | Date: | 24.04.1991 | Language: | EN | [1991/17] | Type: | A3 Search report | No.: | EP0423826 | Date: | 07.08.1991 | Language: | EN | [1991/32] | Type: | B1 Patent specification | No.: | EP0423826 | Date: | 17.07.1996 | Language: | EN | [1996/29] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 18.06.1991 | Classification | IPC: | H01L27/092 | [1991/17] | CPC: |
H01L27/092 (EP,US)
| Designated contracting states | DE, FR, GB [1991/17] | Title | German: | Integrierte MOS-Schaltung | [1991/17] | English: | MOS-type integrated circuit | [1991/17] | French: | Circuit intégré du type MOS | [1991/17] | Examination procedure | 19.10.1990 | Examination requested [1991/17] | 15.07.1993 | Despatch of a communication from the examining division (Time limit: M04) | 29.07.1994 | Despatch of a communication from the examining division (Time limit: M04) | 25.10.1994 | Reply to a communication from the examining division | 13.10.1995 | Despatch of communication of intention to grant (Approval: Yes) | 23.01.1996 | Communication of intention to grant the patent | 16.04.1996 | Fee for grant paid | 16.04.1996 | Fee for publishing/printing paid | Opposition(s) | 18.04.1997 | No opposition filed within time limit [1997/28] | Fees paid | Renewal fee | 09.10.1992 | Renewal fee patent year 03 | 11.10.1993 | Renewal fee patent year 04 | 08.10.1994 | Renewal fee patent year 05 | 10.10.1995 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A] - MICROELECTRONICS JOURNAL. SPRING vol. 20, no. 1-2, 1989, LUTON GB pages 77 - 103; P. ROSSEL et al.: "SMART POWER AND HIGH VOLTAGE INTEGRATED CIRCUITS AND RELATED MOS TECHNOLOGIES" | [A] - NEW ELECTRONICS.INCORPORATING ELECTRONICS TODAY. vol. 20, no. 12, 1987, LONDON GB pages 24 - 27; E. WILLIAMS et al.: "D/CMOS PROCESSES FOR ANALOGUE MULTIPLEXERS" |