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EP0427245
European procedure
Extract from the Register of European Patents
EP About this file: EP0427245
| EP0427245 - Data processor capable of simultaneously executing two instructions [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 29.01.1999 Database last updated on 03.10.2024 | Most recent event Tooltip | 29.01.1999 | No opposition filed within time limit | published on 17.03.1999 [1999/11] | Applicant(s) | For all designated states Hitachi, Ltd. 6, Kanda Surugadai 4-chome Chiyoda-ku Tokyo / JP | [N/P] |
| Former [1991/20] | For all designated states HITACHI, LTD. 6, Kanda Surugadai 4-chome Chiyoda-ku, Tokyo 100 / JP | Inventor(s) | 01 /
Hanawa, Makoto 1-3, Higashikoigakubo-3-chome Kokubunji-shi / JP | 02 /
Nishimukai, Tadahiko 3-39, Nishihashimoto-1-chome Sagamihara-shi / JP | [1991/20] | Representative(s) | Strehl Schübel-Hopf & Partner Maximilianstrasse 54 80538 München / DE | [N/P] |
| Former [1991/20] | Strehl Schübel-Hopf Groening & Partner Maximilianstrasse 54 D-80538 München / DE | Application number, filing date | 90121337.1 | 07.11.1990 | [1991/20] | Priority number, date | JP19890288874 | 08.11.1989 Original published format: JP 28887489 | [1991/20] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0427245 | Date: | 15.05.1991 | Language: | EN | [1991/20] | Type: | A3 Search report | No.: | EP0427245 | Date: | 29.01.1992 | Language: | EN | [1992/05] | Type: | B1 Patent specification | No.: | EP0427245 | Date: | 25.03.1998 | Language: | EN | [1998/13] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 12.12.1991 | Classification | IPC: | G06F9/38 | [1991/20] | CPC: |
G06F9/3826 (EP,US);
G06F9/38 (KR);
G06F9/30167 (EP,US);
G06F9/3822 (EP,US);
G06F9/3824 (EP,US)
| Designated contracting states | DE, FR, GB, IT [1991/20] | Title | German: | Datenprozessor mit der Fähigkeit, zwei Befehle gleichzeitig auszuführen | [1991/20] | English: | Data processor capable of simultaneously executing two instructions | [1991/20] | French: | Processeur de données capable d'exécuter simultanément deux instructions | [1991/20] | Examination procedure | 01.06.1992 | Examination requested [1992/32] | 29.03.1996 | Despatch of a communication from the examining division (Time limit: M06) | 07.10.1996 | Reply to a communication from the examining division | 23.04.1997 | Despatch of communication of intention to grant (Approval: No) | 23.09.1997 | Despatch of communication of intention to grant (Approval: later approval) | 26.09.1997 | Communication of intention to grant the patent | 29.12.1997 | Fee for grant paid | 29.12.1997 | Fee for publishing/printing paid | Opposition(s) | 29.12.1998 | No opposition filed within time limit [1999/11] | Fees paid | Renewal fee | 27.11.1992 | Renewal fee patent year 03 | 29.11.1993 | Renewal fee patent year 04 | 28.11.1994 | Renewal fee patent year 05 | 27.11.1995 | Renewal fee patent year 06 | 26.11.1996 | Renewal fee patent year 07 | 27.11.1997 | Renewal fee patent year 08 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [Y]EP0269980 (HITACHI LTD [JP]); | [Y]EP0260409 (IBM [US]) | [A] - IBM TECHNICAL DISCLOSURE BULLETIN. vol. 29, no. 2, July 1986, NEW YORK US pages 605 - 608; 'Data Bypass Methodology for a Performance Pipeline Processor' | [A] - IEEE TRANSACTIONS ON COMPUTERS. vol. 38, no. 2, February 1989, NEW YORK US pages 263 - 274; W. HELBIG, V. MILUTINOVIC: 'A DCFL E/D-MESFET GaAs Experimental RISC Machine' |