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Extract from the Register of European Patents

EP About this file: EP0430147

EP0430147 - Semiconductor gate array device compatible with ECL signals and/or TTL signals [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  21.04.1995
Database last updated on 06.07.2024
Most recent event   Tooltip21.04.1995Application deemed to be withdrawnpublished on 14.06.1995 [1995/24]
Applicant(s)For all designated states
Hitachi, Ltd.
6, Kanda Surugadai 4-chome
Chiyoda-ku
Tokyo / JP
For all designated states
HITACHI MICROCOMPUTER SYSTEM LTD.
5-22-1, Josuihon-cho Kodaira-shi
Tokyo / JP
[N/P]
Former [1991/23]For all designated states
HITACHI, LTD.
6, Kanda Surugadai 4-chome
Chiyoda-ku, Tokyo 100 / JP
For all designated states
HITACHI MICROCOMPUTER SYSTEM LTD.
5-22-1, Josuihon-cho
Kodaira-shi, Tokyo / JP
Inventor(s)01 / Tsuru, Yoshihiro, B-102, Hitachimaikon
gakuendai2shataku, 3-1620, Gakuennishi-machi
Kodaira-shi, Tokyo / JP
02 / Kuraishi, Takashi, B-105
Hitachimaikon-reimeiryo, 11, Shimotaki-machi
Takasaki-shi, Gunma / JP
03 / Matsuzaki, Fumiaki, A-105
Hitachimaikon-reimeiryo, 11, Shimotaki-machi
Takasaki-shi, Gunma / JP
04 / Morishige, Takaharu
109, Hitachimaikon-kaminakaishataku, 381
Kaminakai-machi, Takasaki-shi, Gunma / JP
[1991/23]
Representative(s)Strehl Schübel-Hopf & Partner
Maximilianstrasse 54
80538 München / DE
[N/P]
Former [1991/23]Strehl Schübel-Hopf Groening & Partner
Maximilianstrasse 54
D-80538 München / DE
Application number, filing date90122572.226.11.1990
[1991/23]
Priority number, dateJP1989030697227.11.1989         Original published format: JP 30697289
[1991/23]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0430147
Date:05.06.1991
Language:EN
[1991/23]
Type: A3 Search report 
No.:EP0430147
Date:19.11.1992
Language:EN
[1992/47]
Search report(s)(Supplementary) European search report - dispatched on:EP28.09.1992
ClassificationIPC:H01L27/118
[1991/23]
CPC:
H01L27/11898 (EP,US); H03K19/00 (KR)
Designated contracting statesDE,   FR,   GB,   IT [1991/23]
TitleGerman:Gatearray-Halbleitervorrichtung kompatibel mit ECL- und/oder TTL-Signalen[1991/23]
English:Semiconductor gate array device compatible with ECL signals and/or TTL signals[1991/23]
French:Dispositif semi-conducteur à matrice de portes compatible avec des signaux ECL et/ou des signaux TTL[1991/23]
File destroyed:03.03.2001
Examination procedure14.05.1993Examination requested  [1993/29]
27.07.1994Despatch of a communication from the examining division (Time limit: M04)
07.12.1994Application deemed to be withdrawn, date of legal effect  [1995/24]
10.01.1995Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time  [1995/24]
Fees paidRenewal fee
27.11.1992Renewal fee patent year 03
29.11.1993Renewal fee patent year 04
28.11.1994Renewal fee patent year 05
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Documents cited:Search[Y]JP58012346
 [Y]  - PATENT ABSTRACT OF JAPAN, vol. 7, no. 84 (E-169)(1229), 8th April 1983; & JP-A-58 012 346 (NIPPON DENKI K.K.) 24-01-1983, & JP58012346 A 00000000
 [Y]  - PROC. OF THE IEEE 1989 CUSTOM INTEGRATED CIRCUITS CONFERENCE, California, US, 15th - 18th May 1989, pages 841-844; A. DENDA et al.: "A 270 ps / 24.000 gate BiCMOS gate array"
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.