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EP0437834
European procedure
Extract from the Register of European Patents
EP About this file: EP0437834
| EP0437834 - Method for manufacturing a semiconductor integrated circuit [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 17.01.1997 Database last updated on 18.11.2024 | Most recent event Tooltip | 17.01.1997 | No opposition filed within time limit | published on 05.03.1997 [1997/10] | Applicant(s) | For all designated states SANYO ELECTRIC CO., LTD. 2-18, Keihan-Hondori Moriguchi-shi, Osaka / JP | [1991/30] | Inventor(s) | 01 /
Takeda, Kazuo 32-7, Kanayama-machi Outa-shi, Gunma / JP | 02 /
Sekikawa, Nobuyuki 8-101, Izumi-Ryo, 57-1, Sumiyoshi Ouizumi-machi, Oura-gun, Gunma / JP | 03 /
Tabata, Teruo 624-7, Shimokoizumi, Ouizumi-machi Oura-gun, Gunma / JP | 04 /
Sano, Yoshiaki Izumi-Ryo 1939-24, Shimokoizumi Ouizumi-machi, Oura-gun, Gunma / JP | [1991/30] | Representative(s) | Wächtershäuser, Günter Wächtershäuser & Hartz Patentanwälte Ottostrasse 4 80333 München / DE | [N/P] |
| Former [1991/30] | Wächtershäuser, Günter, Prof. Dr. Patentanwalt, Tal 29 D-80331 München / DE | Application number, filing date | 90125499.5 | 27.12.1990 | [1991/30] | Priority number, date | JP19890340810 | 28.12.1989 Original published format: JP 34081089 | JP19890340813 | 28.12.1989 Original published format: JP 34081389 | JP19890340814 | 28.12.1989 Original published format: JP 34081489 | JP19890340816 | 28.12.1989 Original published format: JP 34081689 | [1991/30] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0437834 | Date: | 24.07.1991 | Language: | EN | [1991/30] | Type: | B1 Patent specification | No.: | EP0437834 | Date: | 13.03.1996 | Language: | EN | [1996/11] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 21.05.1991 | Classification | IPC: | H01L21/266, H01L21/82, H01L21/331, H01L21/033, H01L21/76 | [1996/11] | CPC: |
H01L21/033 (EP);
H01L21/761 (EP);
H01L21/8224 (EP);
H01L21/8226 (EP)
|
| Former IPC [1991/30] | H01L21/266, H01L21/82, H01L21/331 | Designated contracting states | DE, FR, IT, NL [1991/30] | Title | German: | Verfahren zur Herstellung einer integrierten Halbleiterschaltung | [1991/30] | English: | Method for manufacturing a semiconductor integrated circuit | [1991/30] | French: | Procédé pour la fabrication d'un circuit intégré à semiconducteur | [1991/30] | Examination procedure | 23.01.1992 | Examination requested [1992/13] | 21.03.1994 | Despatch of a communication from the examining division (Time limit: M04) | 21.06.1994 | Despatch of a communication from the examining division (Time limit: M06) | 02.01.1995 | Reply to a communication from the examining division | 21.02.1995 | Despatch of communication of intention to grant (Approval: Yes) | 27.06.1995 | Communication of intention to grant the patent | 25.09.1995 | Fee for grant paid | 25.09.1995 | Fee for publishing/printing paid | Opposition(s) | 14.12.1996 | No opposition filed within time limit [1997/10] | Fees paid | Renewal fee | 29.12.1992 | Renewal fee patent year 03 | 28.09.1993 | Renewal fee patent year 04 | 28.09.1994 | Renewal fee patent year 05 | 22.12.1995 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]US3933528 ; | [Y]US4780425 ; | [Y]US3915766 ; | [X]FR2260186 ; | [X]EP0007923 ; | [A]EP0005164 | Examination | - Latest LSI Process Technology, April 25, 1984, published by the Industrial Board of Inquiry, Japan (relevant pages filed by the applicant with letter dated 2.1.95) |