-
EP0422912
European procedure
Extract from the Register of European Patents
EP About this file: EP0422912
| EP0422912 - Semiconductor integrated circuit device having test circuit [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 14.03.1997 Database last updated on 19.07.2024 | Most recent event Tooltip | 14.03.1997 | No opposition filed within time limit | published on 02.05.1997 [1997/18] | Applicant(s) | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi Kanagawa 211 / JP | [N/P] |
| Former [1991/16] | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 / JP | Inventor(s) | 01 /
Shikatani, Junichi 142-202, Miyauchi Kawasaki-shi Kanagawa, 211 / JP | [1991/16] | Representative(s) | Billington, Lawrence Emlyn, et al Haseltine Lake LLP Lincoln House, 5th Floor 300 High Holborn London WC1V 7JH / GB | [N/P] |
| Former [1991/16] | Billington, Lawrence Emlyn, et al Haseltine Lake & Co Hazlitt House 28, Southampton Buildings Chancery Lane London WC2A 1AT / GB | Application number, filing date | 90311092.2 | 10.10.1990 | [1991/16] | Priority number, date | JP19890266662 | 13.10.1989 Original published format: JP 26666289 | [1991/16] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0422912 | Date: | 17.04.1991 | Language: | EN | [1991/16] | Type: | A3 Search report | No.: | EP0422912 | Date: | 27.05.1992 | Language: | EN | [1992/22] | Type: | B1 Patent specification | No.: | EP0422912 | Date: | 08.05.1996 | Language: | EN | [1996/19] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 08.04.1992 | Classification | IPC: | G06F11/26 | [1996/19] | CPC: |
H03K19/17772 (EP,US);
G01R31/36 (KR);
G01R31/318516 (EP,US);
G11C7/1006 (EP,US);
H03K19/17704 (EP,US);
H03K19/17728 (EP,US);
|
| Former IPC [1991/16] | G01R31/318 | Designated contracting states | DE, FR, GB [1991/16] | Title | German: | Integriertes Halbleiterschaltungsgerät mit Prüfschaltung | [1991/16] | English: | Semiconductor integrated circuit device having test circuit | [1991/16] | French: | Dispositif de circuit intégré à semi-conducteur comportant un circuit de test | [1991/16] | Examination procedure | 30.06.1992 | Examination requested [1992/35] | 17.08.1994 | Despatch of a communication from the examining division (Time limit: M06) | 30.12.1994 | Reply to a communication from the examining division | 08.08.1995 | Despatch of communication of intention to grant (Approval: Yes) | 06.11.1995 | Communication of intention to grant the patent | 30.01.1996 | Fee for grant paid | 30.01.1996 | Fee for publishing/printing paid | Opposition(s) | 11.02.1997 | No opposition filed within time limit [1997/18] | Fees paid | Renewal fee | 30.09.1992 | Renewal fee patent year 03 | 15.10.1993 | Renewal fee patent year 04 | 06.10.1994 | Renewal fee patent year 05 | 23.10.1995 | Renewal fee patent year 06 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [AD]EP0174236 (FUJITSU LTD [JP]); | [A]EP0223714 (FUJITSU LTD [JP]) | [A] - PROCEEDINGS OF THE 26TH DESIGN AUTOMATION CONFE- RENCE, June 25-29, 1989, pages 706-709, IEEE, New York, US; T. GHEEWALA:'CrossCheck: A cell based VLSI testability solution' |