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Extract from the Register of European Patents

EP About this file: EP0449218

EP0449218 - Semiconductor memory device having signal receiving facility fabricated from BI-CMOS circuits [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  16.05.1997
Database last updated on 14.09.2024
Most recent event   Tooltip16.05.1997No opposition filed within time limitpublished on 02.07.1997 [1997/27]
Applicant(s)For all designated states
NEC Corporation
7-1, Shiba 5-chome Minato-ku
Tokyo 108-8001 / JP
[N/P]
Former [1991/40]For all designated states
NEC CORPORATION
7-1, Shiba 5-chome Minato-ku
Tokyo / JP
Inventor(s)01 / Shimogawa, Kenjyu, c/o NEC Corporation
7-1, Shiba 5-chome
Minato-ku, Tokyo / JP
[1991/40]
Representative(s)Glawe, Delfs, Moll
Partnerschaft mbB von
Patent- und Rechtsanwälten
Postfach 26 01 62
80058 München / DE
[N/P]
Former [1991/40]Glawe, Delfs, Moll & Partner
Patentanwälte Postfach 26 01 62
D-80058 München / DE
Application number, filing date91104791.826.03.1991
[1991/40]
Priority number, dateJP1990008268329.03.1990         Original published format: JP 8268390
[1991/40]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0449218
Date:02.10.1991
Language:EN
[1991/40]
Type: A3 Search report 
No.:EP0449218
Date:17.03.1993
Language:EN
[1993/11]
Type: B1 Patent specification 
No.:EP0449218
Date:10.07.1996
Language:EN
[1996/28]
Search report(s)(Supplementary) European search report - dispatched on:EP22.01.1993
ClassificationIPC:G11C5/14, G11C11/418
[1996/28]
CPC:
G11C11/418 (EP,US); G11C5/143 (EP,US)
Former IPC [1991/40]G11C11/418
Designated contracting statesDE,   FR,   GB [1991/40]
TitleGerman:Halbleiterspeicheranordnung hergestellt mit BICMOS-Schaltungen und fähig, ein Signal zu empfangen[1991/40]
English:Semiconductor memory device having signal receiving facility fabricated from BI-CMOS circuits[1991/40]
French:Dispositif de mémoire à semi-conducteurs fabriqué avec des circuits BI-CMOS avec facilité de réception de signal[1991/40]
Examination procedure26.03.1991Examination requested  [1991/40]
08.12.1994Despatch of a communication from the examining division (Time limit: M06)
13.06.1995Reply to a communication from the examining division
08.09.1995Despatch of communication of intention to grant (Approval: Yes)
16.01.1996Communication of intention to grant the patent
19.04.1996Fee for grant paid
19.04.1996Fee for publishing/printing paid
Opposition(s)11.04.1997No opposition filed within time limit [1997/27]
Fees paidRenewal fee
19.03.1993Renewal fee patent year 03
21.03.1994Renewal fee patent year 04
17.03.1995Renewal fee patent year 05
15.03.1996Renewal fee patent year 06
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Documents cited:Search[A]JP5651090  ;
 [A]JP5794984  ;
 [A]JP5310229
 [Y]  - IEEE JOURNAL OF SOLID-STATE CIRCUITS. vol. 23, no. 5, October 1988, NEW YORK US pages 1048 - 1053 KERTIS ET AL 'A 12-ns ECL I/O 256Kx1-bit SRAM using a 1-um BiCMOS Technology'
 [Y]  - IEEE JOURNAL OF SOLID-STATE CIRCUITS. vol. 21, no. 5, October 1986, NEW YORK US pages 692 - 703 FLANNAGAN ET AL 'Two 13-ns 64K CMOS SRAMs with Very Low Active Power and Improved Asynchronous Circuit Techniques'
 [A]  - IEEE INTERNATIONAL SOLID STATE CIRCUITS CONFERENCE. vol. 37, 15 February 1990, NEW YORK US pages 138 - 139 TAKADA ET AL 'A 5ns 1Mb ECL BiCMOS SRAM'
 [A]  - PATENT ABSTRACTS OF JAPAN vol. 5, no. 107 (P-70)(779) 11 July 1981 & JP-A-56 51 090 ( TOKYO SHIBAURA DENKI ) 8 May 1981, & JP5651090 A 19810508
 [A]  - PATENT ABSTRACTS OF JAPAN vol. 6, no. 179 (P-142)(1057) 14 September 1982 & JP-A-57 94 984 ( SANYO DENKI KK ) 12 June 1982, & JP5794984 A 19820612
 [A]  - PATENT ABSTRACTS OF JAPAN vol. 2, no. 45 (E-24)27 March 1978 & JP-A-53 10 229 ( MITSUBISHI DENKI KK ) 30 January 1978, & JP5310229 A 19780130
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.