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EP0453998
European procedure
Extract from the Register of European Patents
EP About this file: EP0453998
| EP0453998 - Semiconductor memory device having a bit line constituted by a semiconductor layer [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 08.05.1998 Database last updated on 27.07.2024 | Most recent event Tooltip | 21.06.2002 | Lapse of the patent in a contracting state | published on 07.08.2002 [2002/32] | Applicant(s) | For all designated states Kabushiki Kaisha Toshiba 72, Horikawa-cho, Saiwai-ku Kawasaki-shi Kanagawa-ken 210-8572 / JP | [N/P] |
| Former [1995/01] | For all designated states KABUSHIKI KAISHA TOSHIBA 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210, Tokyo / JP | ||
| Former [1991/44] | For all designated states Kabushiki Kaisha Toshiba 72, Horikawa-cho Saiwai-ku Kawasaki-shi / JP | Inventor(s) | 01 /
Kumagai, Jumpei, c/o Intellectual Property Div. K.K. TOSHIBA, 1-1 Shibaura 1-chome Minato-ku, Tokyo 105 / JP | 02 /
Sawada, Shizuo, c/o Intellectual Property Div. K.K. TOSHIBA, 1-1 Shibaura 1-chome Minato-ku, Tokyo 105 / JP | [1991/44] | Representative(s) | Lehn, Werner, et al Hoffmann Eitle, Patent- und Rechtsanwälte, Postfach 81 04 20 81904 München / DE | [N/P] |
| Former [1991/44] | Lehn, Werner, Dipl.-Ing., et al Hoffmann, Eitle & Partner, Patentanwälte, Postfach 81 04 20 D-81904 München / DE | Application number, filing date | 91106366.7 | 19.04.1991 | [1991/44] | Priority number, date | JP19900105911 | 21.04.1990 Original published format: JP 10591190 | [1991/44] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0453998 | Date: | 30.10.1991 | Language: | EN | [1991/44] | Type: | B1 Patent specification | No.: | EP0453998 | Date: | 02.07.1997 | Language: | EN | [1997/27] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 24.07.1991 | Classification | IPC: | H01L27/108, H01L21/8242 | [1997/27] | CPC: |
H10B12/34 (EP);
H10B12/00 (KR);
H10B12/0383 (EP);
H10B12/395 (EP)
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| Former IPC [1991/44] | H01L27/108 | Designated contracting states | DE, FR, GB [1991/44] | Title | German: | Halbleiterspeicherbauteil mit Bitleitung, welche aus einer Halbleiterschicht besteht | [1991/44] | English: | Semiconductor memory device having a bit line constituted by a semiconductor layer | [1991/44] | French: | Dispositif semi-conducteur à mémoire ayant une ligne de bit constituée d'une couche semi-conductrice | [1991/44] | Examination procedure | 19.04.1991 | Examination requested [1991/44] | 22.04.1994 | Despatch of a communication from the examining division (Time limit: M04) | 12.08.1994 | Reply to a communication from the examining division | 13.03.1995 | Despatch of a communication from the examining division (Time limit: M06) | 12.09.1995 | Reply to a communication from the examining division | 20.06.1996 | Despatch of communication of intention to grant (Approval: Yes) | 09.10.1996 | Communication of intention to grant the patent | 02.01.1997 | Fee for grant paid | 02.01.1997 | Fee for publishing/printing paid | Opposition(s) | 03.04.1998 | No opposition filed within time limit [1998/26] | Fees paid | Renewal fee | 13.04.1993 | Renewal fee patent year 03 | 11.04.1994 | Renewal fee patent year 04 | 04.04.1995 | Renewal fee patent year 05 | 16.04.1996 | Renewal fee patent year 06 | 12.04.1997 | Renewal fee patent year 07 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | FR | 02.07.1997 | [2002/32] | Documents cited: | Search | [A]JP1248557 ; | [A]JP1198065 ; | [X]JP2026066 ; | [X]EP0042084 (IBM [US]); | [X]US4829017 (MALHI SATWINDER S [US]); | [X]US4845537 (NISHIMURA TADASHI [JP], et al) | Examination | EP0348046 |