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EP0464837
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EP About this file: EP0464837
| EP0464837 - Method of manufacturing semiconductor substrate using semiconductor integrated circuit having dielectric separation structure [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 10.01.1996 Database last updated on 03.08.2024 | Most recent event Tooltip | 10.01.1996 | Application deemed to be withdrawn | published on 21.02.1996 [1996/08] | Applicant(s) | For all designated states Kabushiki Kaisha Toshiba 72, Horikawa-cho, Saiwai-ku Kawasaki-shi Kanagawa-ken 210-8572 / JP | [N/P] |
| Former [1995/01] | For all designated states KABUSHIKI KAISHA TOSHIBA 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210, Tokyo / JP | ||
| Former [1992/02] | For all designated states KABUSHIKI KAISHA TOSHIBA 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210 / JP | Inventor(s) | 01 /
Hoshi, Tadahide 6-25-205, Toyooka-Cho, Tsurumi-Ku Yokohama-Shi, Kanagawa-Ken / JP | [1992/02] | Representative(s) | Lehn, Werner, et al Hoffmann Eitle, Patent- und Rechtsanwälte, Postfach 81 04 20 81904 München / DE | [N/P] |
| Former [1992/02] | Lehn, Werner, Dipl.-Ing., et al Hoffmann, Eitle & Partner, Patentanwälte, Postfach 81 04 20 D-81904 München / DE | Application number, filing date | 91111196.1 | 05.07.1991 | [1992/02] | Priority number, date | JP19900177883 | 05.07.1990 Original published format: JP 17788390 | [1992/02] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0464837 | Date: | 08.01.1992 | Language: | EN | [1992/02] | Type: | A3 Search report | No.: | EP0464837 | Date: | 27.01.1993 | Language: | EN | [1993/04] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 09.12.1992 | Classification | IPC: | H01L21/76, H01L21/20 | [1993/04] | CPC: |
H01L21/2007 (EP);
H01L21/304 (KR);
H01L21/76264 (EP);
H01L21/76275 (EP);
H01L21/76286 (EP)
|
| Former IPC [1992/02] | H01L21/76 | Designated contracting states | DE, FR, GB [1992/02] | Title | German: | Verfahren zur Herstellung eines Halbleitersubstrats unter Verwendung einer halbleiterintegrierten Schaltung mit einer dielektrischen Isolationsstruktur | [1992/02] | English: | Method of manufacturing semiconductor substrate using semiconductor integrated circuit having dielectric separation structure | [1992/02] | French: | Procédé pour fabriquer un substrat semi-conducteur utilisant un circuit intégré semi-conducteur comportant une structure de séparation diélectrique | [1992/02] | File destroyed: | 20.04.2002 | Examination procedure | 05.07.1991 | Examination requested [1992/02] | 05.04.1993 | Despatch of a communication from the examining division (Time limit: M06) | 15.10.1993 | Reply to a communication from the examining division | 14.02.1995 | Despatch of a communication from the examining division (Time limit: M06) | 25.08.1995 | Application deemed to be withdrawn, date of legal effect [1996/08] | 25.09.1995 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time [1996/08] | Fees paid | Renewal fee | 12.07.1993 | Renewal fee patent year 03 | 07.07.1994 | Renewal fee patent year 04 | 11.07.1995 | Renewal fee patent year 05 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]US4851078 (SHORT JOHN P [US], et al); | [Y]EP0296754 (TOSHIBA KK [JP]); | [Y]EP0182032 (TOSHIBA KK [JP]) | [X] - GOTOU H., ET AL., "SOI-DEVICE ON BONDED WAFER.", FUJITSU-SCIENTIFIC AND TECHNICAL JOURNAL., Fujitsu Ltd., JP, JP, (19881221), vol. 24., no. 04 + INDEX., ISSN 0016-2523, pages 408 - 417., XP000112818 |