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Extract from the Register of European Patents

EP About this file: EP0481555

EP0481555 - Heterostructure field-effect transistor [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  08.11.1996
Database last updated on 20.07.2024
Most recent event   Tooltip08.11.1996No opposition filed within time limitpublished on 27.12.1996 [1996/52]
Applicant(s)For:GB 
PHILIPS ELECTRONICS UK LIMITED
420-430 London Road
Croydon CR9 3QR / GB
For:DE  FR 
Koninklijke Philips Electronics N.V.
Groenewoudseweg 1
5621 BA Eindhoven / NL
[N/P]
Former [1992/17]For:GB 
PHILIPS ELECTRONICS UK LIMITED
420-430 London Road
Croydon CR9 3QR / GB
For:DE  FR 
Philips Electronics N.V.
Groenewoudseweg 1
NL-5621 BA Eindhoven / NL
Inventor(s)01 / Battersby, Stephen John
c/o Philips Research Lab.
Redhill, Surrey RH1 5HA / GB
[1992/17]
Representative(s)Stevens, Brian Thomas, et al
Philips Electronics UK Limited Patents and Trade Marks Department Cross Oak Lane
Redhill, Surrey RH1 5HA / GB
[1995/10]
Former [1992/17]Clark, Jane Anne
Philips Electronics UK Limited Patents and Trade Marks Department Cross Oak Lane
Redhill, Surrey RH1 5HA / GB
Application number, filing date91202629.110.10.1991
[1992/17]
Priority number, dateGB1990002275619.10.1990         Original published format: GB 9022756
[1992/17]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP0481555
Date:22.04.1992
Language:EN
[1992/17]
Type: B1 Patent specification 
No.:EP0481555
Date:03.01.1996
Language:EN
[1996/01]
Search report(s)(Supplementary) European search report - dispatched on:EP06.02.1992
ClassificationIPC:H01L29/812, H01L29/10, H01L29/205
[1992/17]
CPC:
H01L29/7783 (EP,US); H01L29/1075 (EP,US); H01L29/205 (EP,US)
Designated contracting statesDE,   FR,   GB [1992/17]
TitleGerman:Heterostruktur-Feldeffekttransistor[1992/17]
English:Heterostructure field-effect transistor[1992/17]
French:Transistor à effect de champ à hétérostructure[1992/17]
Examination procedure22.10.1992Examination requested  [1992/51]
11.04.1994Despatch of a communication from the examining division (Time limit: M04)
05.08.1994Reply to a communication from the examining division
11.10.1994Despatch of communication of intention to grant (Approval: Yes)
24.03.1995Despatch of communication that the application is refused, reason: formalities examination {1}
29.05.1995Communication of intention to grant the patent
08.09.1995Fee for grant paid
08.09.1995Fee for publishing/printing paid
Opposition(s)05.10.1996No opposition filed within time limit [1996/52]
Request for further processing for:01.04.1995Request for further processing filed
01.04.1995Full payment received (date of receipt of payment)
Request granted
29.05.1995Decision despatched
Fees paidRenewal fee
25.10.1993Renewal fee patent year 03
26.10.1994Renewal fee patent year 04
31.10.1995Renewal fee patent year 05
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Documents cited:Search[A]JP61144070  ;
 [A]GB2219130  (PHILIPS ELECTRONIC ASSOCIATED [GB]);
 [AD]EP0243953  (SUMITOMO ELECTRIC INDUSTRIES [JP])
 [A]  - PATENT ABSTRACTS OF JAPAN vol. 10, no. 340 (E-455)(2396) 18 November 1986 & JP-A-61 144 070 ( FUJITSU LTD ) 1 July 1986, & JP61144070 A 19860701
 [A]  - ELECTRONICS LETTERS. vol. 26, no. 3, 1 February 1990, STEVENAGE GB pages 161 - 162; A. CAPPY ET AL.: 'Ultra high transconductance 0.25 um gate MESFET with strained InGaAs buffer layer'
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.