EP0481555 - Heterostructure field-effect transistor [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 08.11.1996 Database last updated on 20.07.2024 | Most recent event Tooltip | 08.11.1996 | No opposition filed within time limit | published on 27.12.1996 [1996/52] | Applicant(s) | For:GB
PHILIPS ELECTRONICS UK LIMITED 420-430 London Road Croydon CR9 3QR / GB | For:DE
FR
Koninklijke Philips Electronics N.V. Groenewoudseweg 1 5621 BA Eindhoven / NL | [N/P] |
Former [1992/17] | For:GB
PHILIPS ELECTRONICS UK LIMITED 420-430 London Road Croydon CR9 3QR / GB | ||
For:DE
FR
Philips Electronics N.V. Groenewoudseweg 1 NL-5621 BA Eindhoven / NL | Inventor(s) | 01 /
Battersby, Stephen John c/o Philips Research Lab. Redhill, Surrey RH1 5HA / GB | [1992/17] | Representative(s) | Stevens, Brian Thomas, et al Philips Electronics UK Limited Patents and Trade Marks Department Cross Oak Lane Redhill, Surrey RH1 5HA / GB | [1995/10] |
Former [1992/17] | Clark, Jane Anne Philips Electronics UK Limited Patents and Trade Marks Department Cross Oak Lane Redhill, Surrey RH1 5HA / GB | Application number, filing date | 91202629.1 | 10.10.1991 | [1992/17] | Priority number, date | GB19900022756 | 19.10.1990 Original published format: GB 9022756 | [1992/17] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0481555 | Date: | 22.04.1992 | Language: | EN | [1992/17] | Type: | B1 Patent specification | No.: | EP0481555 | Date: | 03.01.1996 | Language: | EN | [1996/01] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 06.02.1992 | Classification | IPC: | H01L29/812, H01L29/10, H01L29/205 | [1992/17] | CPC: |
H01L29/7783 (EP,US);
H01L29/1075 (EP,US);
H01L29/205 (EP,US)
| Designated contracting states | DE, FR, GB [1992/17] | Title | German: | Heterostruktur-Feldeffekttransistor | [1992/17] | English: | Heterostructure field-effect transistor | [1992/17] | French: | Transistor à effect de champ à hétérostructure | [1992/17] | Examination procedure | 22.10.1992 | Examination requested [1992/51] | 11.04.1994 | Despatch of a communication from the examining division (Time limit: M04) | 05.08.1994 | Reply to a communication from the examining division | 11.10.1994 | Despatch of communication of intention to grant (Approval: Yes) | 24.03.1995 | Despatch of communication that the application is refused, reason: formalities examination {1} | 29.05.1995 | Communication of intention to grant the patent | 08.09.1995 | Fee for grant paid | 08.09.1995 | Fee for publishing/printing paid | Opposition(s) | 05.10.1996 | No opposition filed within time limit [1996/52] | Request for further processing for: | 01.04.1995 | Request for further processing filed | 01.04.1995 | Full payment received (date of receipt of payment) Request granted | 29.05.1995 | Decision despatched | Fees paid | Renewal fee | 25.10.1993 | Renewal fee patent year 03 | 26.10.1994 | Renewal fee patent year 04 | 31.10.1995 | Renewal fee patent year 05 |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]JP61144070 ; | [A]GB2219130 (PHILIPS ELECTRONIC ASSOCIATED [GB]); | [AD]EP0243953 (SUMITOMO ELECTRIC INDUSTRIES [JP]) | [A] - PATENT ABSTRACTS OF JAPAN vol. 10, no. 340 (E-455)(2396) 18 November 1986 & JP-A-61 144 070 ( FUJITSU LTD ) 1 July 1986, & JP61144070 A 19860701 | [A] - ELECTRONICS LETTERS. vol. 26, no. 3, 1 February 1990, STEVENAGE GB pages 161 - 162; A. CAPPY ET AL.: 'Ultra high transconductance 0.25 um gate MESFET with strained InGaAs buffer layer' |