Extract from the Register of European Patents

EP About this file: EP0437371

EP0437371 - Method of manufacturing semiconductor device [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  30.05.1997
Database last updated on 28.03.2026
Most recent event   Tooltip30.05.1997No opposition filed within time limitpublished on 16.07.1997 [1997/29]
Applicant(s)For all designated states
NEC Corporation
7-1, Shiba 5-chome Minato-ku
Tokyo 108-8001 / JP
[N/P]
Former [1991/29]For all designated states
NEC CORPORATION
7-1, Shiba 5-chome Minato-ku
Tokyo / JP
Inventor(s)01 / Nakano, Eiichi
c/o NEC Corporation,7-1, Shiba 5-chome
Minato-ku, Tokyo / JP
[1991/29]
Representative(s)Garratt, Peter Douglas, et al
Mathys & Squire LLP The Shard
32 London Bridge Street
London SE1 9SG / GB
[N/P]
Former [1992/22]Garratt, Peter Douglas, et al
Mathys & Squire 100 Grays Inn Road
London WC1X 8AL / GB
Former [1991/29]Pritchard, Colin Hubert
Mathys & Squire 100 Grays Inn Road
London WC1X 8AL / GB
Application number, filing date91300193.911.01.1991
[1991/29]
Priority number, dateJP1990000510812.01.1990         Original published format: JP 510890
[1991/29]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0437371
Date:17.07.1991
Language:EN
[1991/29]
Type: A3 Search report 
No.:EP0437371
Date:10.06.1992
Language:EN
[1992/24]
Type: B1 Patent specification 
No.:EP0437371
Date:24.07.1996
Language:EN
[1996/30]
Search report(s)(Supplementary) European search report - dispatched on:EP21.04.1992
ClassificationIPC:H01L21/768, H01L21/321
[1996/30]
CPC:
H10W20/056 (EP,US); H10P50/268 (EP,US); Y10S148/131 (EP,US)
Former IPC [1992/24]H01L21/90, H01L21/321
Former IPC [1991/29]H01L21/60, H01L21/90
Designated contracting statesDE,   FR,   GB [1991/29]
TitleGerman:Verfahren zum Herstellen einer Halbleitervorrichtung[1991/29]
English:Method of manufacturing semiconductor device[1991/29]
French:Procédé de fabrication d'un dispositif semi-conducteur[1991/29]
Examination procedure28.01.1991Examination requested  [1991/29]
31.05.1994Despatch of a communication from the examining division (Time limit: M06)
02.12.1994Reply to a communication from the examining division
29.08.1995Despatch of communication of intention to grant (Approval: No)
22.11.1995Despatch of communication of intention to grant (Approval: later approval)
28.11.1995Communication of intention to grant the patent
06.01.1996Fee for grant paid
06.01.1996Fee for publishing/printing paid
Opposition(s)25.04.1997No opposition filed within time limit [1997/29]
Fees paidRenewal fee
11.01.1993Renewal fee patent year 03
22.01.1994Renewal fee patent year 04
21.01.1995Renewal fee patent year 05
24.01.1996Renewal fee patent year 06
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Documents cited:Search[AD]   IEEE 1987 Symposium on VLSI Technology, Karuizawa Japan, 18-21/5/1987, P 103-4, Yoshitaka Narita et.al. "A New CMOS Cell with Fully Planarised Technology".
 [A]   JOURNAL OF THE ELECTROCHEMICAL SOCIETY. vol. 135, no. 10, October 1988, MANCHESTER, NEW HAMPSHIRE US pages 2640 - 2643; N.F. RALEY AND D.L. LOSEE: 'Fabrication of low-resistance polysilicon via plugs in borophosphosilicate glass'
 [AD]   JOURNAL OF THE ELECTROCHEMICAL SOCIETY. vol. 131, no. 8, August 1984, MANCHESTER, NEW HAMPSHIRE US pages 1426 - 1431; S.E. BERNACKI AND B.B. KOSIKI: 'Controlled Film Formation during CCL4 Plasma Etching' [AD]
Examination  MANCHESTER, NEW HAMPSHIRE US pages 1426 - 1431; S.E. BERNACKI AND B.B. KOSIKI: 'Controlled Film Formation during CCL4 Plasma Etching'
   Glow discharge processes, sputtering and plasma etching, B.Chapman, J.Wiley and Sons, USA, 1980.
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