| EP0437371 - Method of manufacturing semiconductor device [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 30.05.1997 Database last updated on 28.03.2026 | Most recent event Tooltip | 30.05.1997 | No opposition filed within time limit | published on 16.07.1997 [1997/29] | Applicant(s) | For all designated states NEC Corporation 7-1, Shiba 5-chome Minato-ku Tokyo 108-8001 / JP | [N/P] |
| Former [1991/29] | For all designated states NEC CORPORATION 7-1, Shiba 5-chome Minato-ku Tokyo / JP | Inventor(s) | 01 /
Nakano, Eiichi c/o NEC Corporation,7-1, Shiba 5-chome Minato-ku, Tokyo / JP | [1991/29] | Representative(s) | Garratt, Peter Douglas, et al Mathys & Squire LLP The Shard 32 London Bridge Street London SE1 9SG / GB | [N/P] |
| Former [1992/22] | Garratt, Peter Douglas, et al Mathys & Squire 100 Grays Inn Road London WC1X 8AL / GB | ||
| Former [1991/29] | Pritchard, Colin Hubert Mathys & Squire 100 Grays Inn Road London WC1X 8AL / GB | Application number, filing date | 91300193.9 | 11.01.1991 | [1991/29] | Priority number, date | JP19900005108 | 12.01.1990 Original published format: JP 510890 | [1991/29] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0437371 | Date: | 17.07.1991 | Language: | EN | [1991/29] | Type: | A3 Search report | No.: | EP0437371 | Date: | 10.06.1992 | Language: | EN | [1992/24] | Type: | B1 Patent specification | No.: | EP0437371 | Date: | 24.07.1996 | Language: | EN | [1996/30] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 21.04.1992 | Classification | IPC: | H01L21/768, H01L21/321 | [1996/30] | CPC: |
H10W20/056 (EP,US);
H10P50/268 (EP,US);
Y10S148/131 (EP,US)
|
| Former IPC [1992/24] | H01L21/90, H01L21/321 | ||
| Former IPC [1991/29] | H01L21/60, H01L21/90 | Designated contracting states | DE, FR, GB [1991/29] | Title | German: | Verfahren zum Herstellen einer Halbleitervorrichtung | [1991/29] | English: | Method of manufacturing semiconductor device | [1991/29] | French: | Procédé de fabrication d'un dispositif semi-conducteur | [1991/29] | Examination procedure | 28.01.1991 | Examination requested [1991/29] | 31.05.1994 | Despatch of a communication from the examining division (Time limit: M06) | 02.12.1994 | Reply to a communication from the examining division | 29.08.1995 | Despatch of communication of intention to grant (Approval: No) | 22.11.1995 | Despatch of communication of intention to grant (Approval: later approval) | 28.11.1995 | Communication of intention to grant the patent | 06.01.1996 | Fee for grant paid | 06.01.1996 | Fee for publishing/printing paid | Opposition(s) | 25.04.1997 | No opposition filed within time limit [1997/29] | Fees paid | Renewal fee | 11.01.1993 | Renewal fee patent year 03 | 22.01.1994 | Renewal fee patent year 04 | 21.01.1995 | Renewal fee patent year 05 | 24.01.1996 | Renewal fee patent year 06 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [AD] IEEE 1987 Symposium on VLSI Technology, Karuizawa Japan, 18-21/5/1987, P 103-4, Yoshitaka Narita et.al. "A New CMOS Cell with Fully Planarised Technology". | [A] JOURNAL OF THE ELECTROCHEMICAL SOCIETY. vol. 135, no. 10, October 1988, MANCHESTER, NEW HAMPSHIRE US pages 2640 - 2643; N.F. RALEY AND D.L. LOSEE: 'Fabrication of low-resistance polysilicon via plugs in borophosphosilicate glass' | [AD] JOURNAL OF THE ELECTROCHEMICAL SOCIETY. vol. 131, no. 8, August 1984, MANCHESTER, NEW HAMPSHIRE US pages 1426 - 1431; S.E. BERNACKI AND B.B. KOSIKI: 'Controlled Film Formation during CCL4 Plasma Etching' [AD] | Examination | MANCHESTER, NEW HAMPSHIRE US pages 1426 - 1431; S.E. BERNACKI AND B.B. KOSIKI: 'Controlled Film Formation during CCL4 Plasma Etching' | Glow discharge processes, sputtering and plasma etching, B.Chapman, J.Wiley and Sons, USA, 1980. |