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EP0462866
European procedure
Extract from the Register of European Patents
EP About this file: EP0462866
| EP0462866 - Semiconductor memory device [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 05.09.1997 Database last updated on 24.08.2024 | Most recent event Tooltip | 17.02.2006 | Change - lapse in a contracting state Updated state(s): FR | published on 05.04.2006 [2006/14] | Applicant(s) | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi Kanagawa 211 / JP | [N/P] |
| Former [1991/52] | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 / JP | Inventor(s) | 01 /
Taguchi, Masao 4-3-4-201, Shin Isono Sagamihara-shi, Kanagawa 228 / JP | [1991/52] | Representative(s) | Joly, Jean-Jacques, et al Cabinet Beau de Loménie 158, rue de l'Université 75340 Paris cedex 07 / FR | [N/P] |
| Former [1991/52] | Joly, Jean-Jacques, et al Cabinet Beau de Loménie 158, rue de l'Université F-75340 Paris Cédex 07 / FR | Application number, filing date | 91401505.2 | 07.06.1991 | [1991/52] | Priority number, date | JP19900149444 | 07.06.1990 Original published format: JP 14944490 | [1991/52] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0462866 | Date: | 27.12.1991 | Language: | EN | [1991/52] | Type: | A3 Search report | No.: | EP0462866 | Date: | 03.02.1993 | Language: | EN | [1993/05] | Type: | B1 Patent specification | No.: | EP0462866 | Date: | 30.10.1996 | Language: | EN | [1996/44] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 17.12.1992 | Classification | IPC: | G11C11/407, G11C11/409 | [1996/44] | CPC: |
G11C5/14 (EP,US);
G11C11/407 (KR);
G11C11/4074 (EP,US);
G11C11/4091 (EP,US);
G11C11/4094 (EP,US);
G11C5/147 (EP,US)
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| Former IPC [1991/52] | G11C11/409 | Designated contracting states | DE, FR, GB, IT [1991/52] | Title | German: | Halbleiterspeicheranordnung | [1991/52] | English: | Semiconductor memory device | [1991/52] | French: | Dispositif de mémoire à semi-conducteurs | [1991/52] | Examination procedure | 06.04.1993 | Examination requested [1993/23] | 16.03.1995 | Despatch of a communication from the examining division (Time limit: M04) | 19.06.1995 | Reply to a communication from the examining division | 18.10.1995 | Despatch of communication of intention to grant (Approval: No) | 25.04.1996 | Despatch of communication of intention to grant (Approval: later approval) | 02.05.1996 | Communication of intention to grant the patent | 18.07.1996 | Fee for grant paid | 18.07.1996 | Fee for publishing/printing paid | Opposition(s) | 31.07.1997 | No opposition filed within time limit [1997/43] | Fees paid | Renewal fee | 18.06.1993 | Renewal fee patent year 03 | 20.06.1994 | Renewal fee patent year 04 | 17.06.1995 | Renewal fee patent year 05 | 21.06.1996 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | FR | 30.10.1996 | [2006/14] |
| Former [1997/34] | FR | 28.03.1997 | Documents cited: | Search | [A] - IEEE INTERNATIONAL SOLID STATE CIRCUITS CONFERENCE. vol. 32, February 1989, NEW YORK US FUJII ET AL. 'A 45NS 16MB DRAM WITH TRIPLE WELL STRUCTURE' PAG 248-249 + 354 | [A] - IEEE JOURNAL OF SOLID-STATE CIRCUITS. vol. 24, no. 3, June 1989, NEW YORK US pages 597 - 602 KITSUKAWA ET AL. 'A 1MBIT BICMOS DRAM USING TEMPERATURE COMPENSATED CIRCUIT TECHNIQUES' | [A] - IEEE JOURNAL OF SOLID-STATE CIRCUITS. vol. 22, no. 3, June 1987, NEW YORK US pages 437 - 441 FURUYAMA ET.AL. 'A NEW ON CHIP VOLTAGE CONVERTERFOR SUB MICROMETER HIGH DENSITY DRAMS' | Examination | EP0129651 |