blank Quick help
blank Maintenance news

Scheduled maintenance

Regular maintenance outages:
between 05.00 and 05.15 hrs CET (Monday to Sunday).

Other outages
Availability
Register Forum

2022.02.11

More...
blank News flashes

News Flashes

New version of the European Patent Register – SPC proceedings information in the Unitary Patent Register.

2024-07-24

More...
blank Related links

Release notes
European Patent Register Assistant
European Patent Register Resource Book
European Patent Register – pocket guide
FAQ - European Patent Register
FAQ - Register Alert
Federated Register (Flyer)
Global Dossier (Flyer)
Register events
Deep link coverage
Federated Register content
The Patent Information Tour
Fair use charter

Extract from the Register of European Patents

EP About this file: EP0584385

EP0584385 - Method and system for testing an integrated circuit featuring scan design [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  12.09.1997
Database last updated on 22.08.2024
Most recent event   Tooltip17.02.2006Change - lapse in a contracting state
Updated state(s): FR		published on 05.04.2006  [2006/14]
Applicant(s)For all designated states
International Business Machines Corporation
Armonk, NY 10504 / US
[N/P]
Former [1994/09]For all designated states
INTERNATIONAL BUSINESS MACHINES CORPORATION
Armonk, NY 10504 / US
Inventor(s)01 / Diebold, Ulrich
Gänsbergring 74
W-7033 Herrenberg / DE
02 / Rost, Peter
In den Lunkteilen 4
W-7260 Calw / DE
03 / Schmidt, Manfred
Dachenhäuserweg 37
W-7036 Schönaich / DE
04 / Torreiter, Otto
Fleinsbachstrasse 14
W-7022 Leinfelden-E / DE
05 / Vogt, Rolf
Herrschaftsgartenstrasse 73
W-7030 Böblingen / DE
06 / Wagner-Drebenstedt, Klaus
Eugenstrasse 19
W-7403 Ammersbuch 1 / DE
[1994/09]
Representative(s)Rach, Werner, et al
IBM Deutschland Management & Business Support GmbH Patentwesen u. Urheberrecht
71137 Ehningen / DE
[N/P]
Former [1996/17]Rach, Werner, Dr., et al
IBM Deutschland Informationssysteme GmbH, Patentwesen und Urheberrecht
D-70548 Stuttgart / DE
Former [1994/38]Schäfer, Wolfgang, Dipl.-Ing.
IBM Deutschland Informationssysteme GmbH Patentwesen und Urheberrecht
D-70548 Stuttgart / DE
Former [1994/09]Mönig, Anton, Dipl.-Ing.
IBM Deutschland Informationssysteme GmbH, Patentwesen und Urheberrecht
D-70548 Stuttgart / DE
Application number, filing date92114431.725.08.1992
[1994/09]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP0584385
Date:02.03.1994
Language:EN
[1994/09]
Type: B1 Patent specification 
No.:EP0584385
Date:06.11.1996
Language:EN
[1996/45]
Search report(s)(Supplementary) European search report - dispatched on:EP25.03.1993
ClassificationIPC:G06F11/26
[1994/09]
CPC:
G01R31/318547 (EP,US); G01R31/318533 (EP,US); G01R31/307 (EP,US)
Designated contracting statesDE,   FR,   GB [1994/09]
TitleGerman:Verfahren und System zum Testen eines integrierten Schaltkreises mit Abfragedesign[1994/09]
English:Method and system for testing an integrated circuit featuring scan design[1994/09]
French:Procédé et système pour tester un circuit intégré avec concept de balayage[1994/09]
Examination procedure27.06.1994Examination requested  [1994/34]
16.03.1995Despatch of a communication from the examining division (Time limit: M06)
28.08.1995Reply to a communication from the examining division
13.12.1995Despatch of communication of intention to grant (Approval: Yes)
11.03.1996Communication of intention to grant the patent
11.06.1996Fee for grant paid
11.06.1996Fee for publishing/printing paid
Opposition(s)07.08.1997No opposition filed within time limit [1997/44]
Fees paidRenewal fee
19.08.1994Renewal fee patent year 03
10.08.1995Renewal fee patent year 04
27.08.1996Renewal fee patent year 05
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipFR06.11.1996
[2006/14]
Former [1997/44]FR04.04.1997
Documents cited:Search[A]  - 13TH ANNUAL SYMPOSIUM ON FAULT-TOLERANT COMPUTING, June 28-30, 1983, pages 222-226 IEEE, New York, US; D.T. TANG et al.: 'Logic test pattern generation using linear codes'
 [A]  - PROCEEDINGS OF THE INTERNATIONAL TEST CON- FERENCE, September 10-14, 1990, pages 670 679, IEEE, New York, US; S. HELLEBRAND: 'Generating pseudo-exhaustive vectors for external testing'
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.