EP0584385 - Method and system for testing an integrated circuit featuring scan design [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 12.09.1997 Database last updated on 22.08.2024 | Most recent event Tooltip | 17.02.2006 | Change - lapse in a contracting state Updated state(s): FR | published on 05.04.2006 [2006/14] | Applicant(s) | For all designated states International Business Machines Corporation Armonk, NY 10504 / US | [N/P] |
Former [1994/09] | For all designated states INTERNATIONAL BUSINESS MACHINES CORPORATION Armonk, NY 10504 / US | Inventor(s) | 01 /
Diebold, Ulrich Gänsbergring 74 W-7033 Herrenberg / DE | 02 /
Rost, Peter In den Lunkteilen 4 W-7260 Calw / DE | 03 /
Schmidt, Manfred Dachenhäuserweg 37 W-7036 Schönaich / DE | 04 /
Torreiter, Otto Fleinsbachstrasse 14 W-7022 Leinfelden-E / DE | 05 /
Vogt, Rolf Herrschaftsgartenstrasse 73 W-7030 Böblingen / DE | 06 /
Wagner-Drebenstedt, Klaus Eugenstrasse 19 W-7403 Ammersbuch 1 / DE | [1994/09] | Representative(s) | Rach, Werner, et al IBM Deutschland Management & Business Support GmbH Patentwesen u. Urheberrecht 71137 Ehningen / DE | [N/P] |
Former [1996/17] | Rach, Werner, Dr., et al IBM Deutschland Informationssysteme GmbH, Patentwesen und Urheberrecht D-70548 Stuttgart / DE | ||
Former [1994/38] | Schäfer, Wolfgang, Dipl.-Ing. IBM Deutschland Informationssysteme GmbH Patentwesen und Urheberrecht D-70548 Stuttgart / DE | ||
Former [1994/09] | Mönig, Anton, Dipl.-Ing. IBM Deutschland Informationssysteme GmbH, Patentwesen und Urheberrecht D-70548 Stuttgart / DE | Application number, filing date | 92114431.7 | 25.08.1992 | [1994/09] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0584385 | Date: | 02.03.1994 | Language: | EN | [1994/09] | Type: | B1 Patent specification | No.: | EP0584385 | Date: | 06.11.1996 | Language: | EN | [1996/45] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 25.03.1993 | Classification | IPC: | G06F11/26 | [1994/09] | CPC: |
G01R31/318547 (EP,US);
G01R31/318533 (EP,US);
G01R31/307 (EP,US)
| Designated contracting states | DE, FR, GB [1994/09] | Title | German: | Verfahren und System zum Testen eines integrierten Schaltkreises mit Abfragedesign | [1994/09] | English: | Method and system for testing an integrated circuit featuring scan design | [1994/09] | French: | Procédé et système pour tester un circuit intégré avec concept de balayage | [1994/09] | Examination procedure | 27.06.1994 | Examination requested [1994/34] | 16.03.1995 | Despatch of a communication from the examining division (Time limit: M06) | 28.08.1995 | Reply to a communication from the examining division | 13.12.1995 | Despatch of communication of intention to grant (Approval: Yes) | 11.03.1996 | Communication of intention to grant the patent | 11.06.1996 | Fee for grant paid | 11.06.1996 | Fee for publishing/printing paid | Opposition(s) | 07.08.1997 | No opposition filed within time limit [1997/44] | Fees paid | Renewal fee | 19.08.1994 | Renewal fee patent year 03 | 10.08.1995 | Renewal fee patent year 04 | 27.08.1996 | Renewal fee patent year 05 |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | FR | 06.11.1996 | [2006/14] |
Former [1997/44] | FR | 04.04.1997 | Documents cited: | Search | [A] - 13TH ANNUAL SYMPOSIUM ON FAULT-TOLERANT COMPUTING, June 28-30, 1983, pages 222-226 IEEE, New York, US; D.T. TANG et al.: 'Logic test pattern generation using linear codes' | [A] - PROCEEDINGS OF THE INTERNATIONAL TEST CON- FERENCE, September 10-14, 1990, pages 670 679, IEEE, New York, US; S. HELLEBRAND: 'Generating pseudo-exhaustive vectors for external testing' |