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Extract from the Register of European Patents

EP About this file: EP0533203

EP0533203 - Method for selectively etching a III-V semiconductor, in the production of a field effect transistor [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  05.12.2003
Database last updated on 06.11.2024
Most recent event   Tooltip05.12.2003Application deemed to be withdrawnpublished on 21.01.2004  [2004/04]
Applicant(s)For all designated states
Sony Corporation
7-35, Kitashinagawa 6-chome
Shinagawa-ku
Tokyo / JP
[N/P]
Former [1993/12]For all designated states
SONY CORPORATION
7-35, Kitashinagawa 6-chome Shinagawa-ku
Tokyo / JP
Inventor(s)01 / Mizunuma, Yasuyuki
c/o Sony Corporation, 7-35 Kitashinagawa 6-chome
Shinagawa-ku, Tokyo / JP
[1993/12]
Representative(s)Müller, Frithjof E.
Müller Hoffmann & Partner Patentanwälte Innere Wiener Strasse 17
81667 München / DE
[N/P]
Former [1997/12]Müller, Frithjof E., Dipl.-Ing.
Patentanwälte MÜLLER & HOFFMANN, Innere Wiener Strasse 17
81667 München / DE
Former [1993/45]TER MEER - MÜLLER - STEINMEISTER & PARTNER
Mauerkircherstrasse 45
D-81679 München / DE
Former [1993/12]Patentanwälte TER MEER - MÜLLER - STEINMEISTER & PARTNER
Mauerkircherstrasse 45
D-81679 München / DE
Application number, filing date92116042.018.09.1992
[1993/12]
Priority number, dateJP1991026853620.09.1991         Original published format: JP 26853691
[1993/12]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0533203
Date:24.03.1993
Language:EN
[1993/12]
Type: A3 Search report 
No.:EP0533203
Date:16.08.1995
Language:EN
[1995/33]
Search report(s)(Supplementary) European search report - dispatched on:EP03.07.1995
ClassificationIPC:H01L21/306, H01L21/335, H01L21/338, H01L21/28
[1995/29]
CPC:
H01L29/66863 (EP,US); H01L21/28587 (EP,US); H01L21/30621 (EP,US);
H01L29/66462 (EP,US); Y10S977/782 (EP,US); Y10S977/815 (EP,US);
Y10S977/888 (EP,US) (-)
Former IPC [1993/12]H01L21/306, H01L21/338, H01L21/28
Designated contracting statesDE,   FR,   GB [1993/12]
TitleGerman:Verfahren zum selektiven Ätzen eines III-V Halbleiters, zur Herstellung eines Feldeffekt-Transistors[1993/12]
English:Method for selectively etching a III-V semiconductor, in the production of a field effect transistor[1993/12]
French:Méthode de gravure sélective d'un semiconducteur III-V, lors de la production d'un transistor à effet de champ[1993/12]
Examination procedure18.01.1996Examination requested  [1996/13]
20.10.1997Despatch of a communication from the examining division (Time limit: M04)
12.11.1997Reply to a communication from the examining division
01.10.1999Despatch of a communication from the examining division (Time limit: M04)
13.01.2000Reply to a communication from the examining division
01.04.2003Application deemed to be withdrawn, date of legal effect  [2004/04]
14.08.2003Despatch of communication that the application is deemed to be withdrawn, reason: renewal fee not paid in time  [2004/04]
Fees paidRenewal fee
08.09.1994Renewal fee patent year 03
08.09.1995Renewal fee patent year 04
12.09.1996Renewal fee patent year 05
10.09.1997Renewal fee patent year 06
09.09.1998Renewal fee patent year 07
13.09.1999Renewal fee patent year 08
13.09.2000Renewal fee patent year 09
12.09.2001Renewal fee patent year 10
Penalty fee
Additional fee for renewal fee
30.09.200211   M06   Not yet paid
30.09.200312   M06   Not yet paid
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[PXPA]JPH04105319  ;
 [XA]EP0348944  (NEC CORP [JP]) [X] 6,10 * page 11, line 40 - line 55; figures 6A-6C * * page 12, line 4 - line 16; figure 7A 7B * * page 12, line 31 - line 33 * [A] 1-5,7-9;
 [XA]EP0244304  (THOMSON CSF [FR]) [X] 6,10 * column 1, line 4 - line 15 * * column 1, line 31 - column 2, line 12 * * column 2, line 55 - column 4, line 30; figures 1,2 * * column 6, line 22 - line 31; figure 5 * [A] 1,2,5,7,9;
 [A]US4992136  (TACHI SHINICHI [JP], et al) [A] 1-4 * column 1, line 25 - line 44 * * column 2, line 15 - line 35; claim 1 * * column 2, line 64 - line 68 *
 [PXA]  - PATENT ABSTRACTS OF JAPAN, (19920724), vol. 016, no. 344, Database accession no. (E - 1239), & JP04105319 A 19920407 (SONY CORP) [PX] 1-6,9 * abstract * [PA] 7,8,10
 [XA]  - S. SALIMIAN ET AL., "Damage studies of dry etched GaAs recessed gates for field effect transistors", JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY: PART B, NEW YORK US, vol. 9, no. 1, pages 114 - 119 [X] 6,10 * page 114; figures 1,2 * [A] 1-4,7,8
 [X]  - PEARTON S J ET AL, "DRY ETCHING OF GAAS, ALGAAS, AND GASB IN HYDROCHLOROFLUOROCARBON MIXTURES", JOURNAL OF THE ELECTROCHEMICAL SOCIETY, vol. 137, no. 12, pages 3892 - 3899 [X] 6 * page 3892; figures 1-4 *
 [A]  - A.E. GEISSBERGER ET AL., "Application of plasma etching to via hole fabrication in thick GaAs substrates.", J. VAC. SCI. TECHNOL, vol. A3, no. 3, pages 863 - 866 [A] 1,3-5,7-9 * page 863, column R; table 1 *
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