-
EP0592715
European procedure
Extract from the Register of European Patents
EP About this file: EP0592715
| EP0592715 - Checking design for testability rules with a VHDL simulator [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 17.04.1998 Database last updated on 02.09.2024 | Most recent event Tooltip | 21.06.2002 | Lapse of the patent in a contracting state New state(s): FR | published on 07.08.2002 [2002/32] | Applicant(s) | For all designated states SIEMENS AKTIENGESELLSCHAFT Werner-von-Siemens-Str. 1 DE-80333 München / DE | [N/P] |
| Former [1994/16] | For all designated states SIEMENS AKTIENGESELLSCHAFT Wittelsbacherplatz 2 D-80333 München / DE | Inventor(s) | 01 /
Glunz, Wolfgang Dipl. Ing. Josef-Bückl-Strasse 32 D-81825 München / DE | [1994/16] | Application number, filing date | 92117650.9 | 15.10.1992 | [1994/16] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0592715 | Date: | 20.04.1994 | Language: | EN | [1994/16] | Type: | B1 Patent specification | No.: | EP0592715 | Date: | 11.06.1997 | Language: | EN | [1997/24] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 02.07.1993 | Classification | IPC: | G06F11/267, G06F17/50 | [1997/24] | CPC: |
G01R31/318357 (EP,US);
G01R31/31704 (EP,US);
G01R31/318364 (EP,US);
G01R31/318583 (EP,US);
G06F30/33 (EP,US)
|
| Former IPC [1994/16] | G06F11/26, G06F15/60 | Designated contracting states | DE, FR, GB [1994/19] |
| Former [1994/16] | AT, BE, CH, DE, DK, ES, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE | Title | German: | Prüfung der prüfgerechten Entwurfsregeln mit einem VHDL-Simulator | [1994/16] | English: | Checking design for testability rules with a VHDL simulator | [1994/16] | French: | Vérification des règles de conception pour la testabilité à l'aide d'un simulateur VHDL | [1994/16] | Examination procedure | 18.10.1993 | Loss of particular rights, legal effect: designated state(s) | 15.12.1993 | Despatch of communication of loss of particular rights: designated state(s) AT, BE, CH, DK, ES, GR, IE, IT, LI, LU | 04.05.1994 | Examination requested [1994/26] | 28.11.1996 | Despatch of communication of intention to grant (Approval: Yes) | 16.12.1996 | Communication of intention to grant the patent | 04.03.1997 | Fee for grant paid | 04.03.1997 | Fee for publishing/printing paid | Opposition(s) | 12.03.1998 | No opposition filed within time limit [1998/23] | Fees paid | Renewal fee | 18.10.1994 | Renewal fee patent year 03 | 20.10.1995 | Renewal fee patent year 04 | 22.10.1996 | Renewal fee patent year 05 | Penalty fee | Penalty fee Rule 85a EPC 1973 | 18.10.1993 | AT M01 Not yet paid | 18.10.1993 | BE M01 Not yet paid | 18.10.1993 | CH M01 Not yet paid | 18.10.1993 | DK M01 Not yet paid | 18.10.1993 | ES M01 Not yet paid | 18.10.1993 | GR M01 Not yet paid | 18.10.1993 | IE M01 Not yet paid | 18.10.1993 | IT M01 Not yet paid | 18.10.1993 | LI M01 Not yet paid | 18.10.1993 | LU M01 Not yet paid | 18.10.1993 | MC M01 Not yet paid | 18.10.1993 | NL M01 Not yet paid | 18.10.1993 | PT M01 Not yet paid | 18.10.1993 | SE M01 Not yet paid |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | FR | 11.06.1997 | DE | 12.09.1997 | GB | 15.10.1997 | [2002/32] |
| Former [1998/41] | DE | 12.09.1997 | |
| GB | 15.10.1997 | ||
| Former [1998/03] | DE | 12.09.1997 | Documents cited: | Search | [AD] - PROCEEDINGS 14TH ACM/IEEE DESIGN AUTOMATION CONFERENCE 1977, US pages 469 - 478 GODOY ET AL 'automatic checking of logic design structures for compliance with testability ground rules' | [AD] - PROCEEDINGS 29TH ACM/IEEE DESIGN AUTOMATION CONFERENCE 8-12 JUNE 1992 ANAHEIM CA US pages 305 - 310 PELZ 'an interpreter for general netlist design rule checking' | [A] - PROCEEDINGS INTERNATIONAL TEST CONFERENCE 1990 IEEE US pages 222 - 234 PARKER ET AL 'a language for describing boundary-scan devices' | Examination | - ET AL 'a language for describing boundary-scan devices' |