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EP0539831
European procedure
Extract from the Register of European Patents
EP About this file: EP0539831
| EP0539831 - Pseudo-NMOS programmable capacitance delay element [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 09.04.1999 Database last updated on 05.10.2024 | Most recent event Tooltip | 09.04.1999 | No opposition filed within time limit | published on 26.05.1999 [1999/21] | Applicant(s) | For all designated states Hewlett-Packard Company 3000 Hanover Street Palo Alto, CA 94304-1112 / US | [N/P] |
| Former [1993/18] | For all designated states Hewlett-Packard Company 3000 Hanover Street Palo Alto, California 94304 / US | Inventor(s) | 01 /
Koerner, Christopher 5699 Boulder Hills Drive Longmont, CO 80503 / US | 02 /
Gutierrez, Albert, Jr. 2606-D Davidson Drive Fort Collins, CO 80526 / US | 03 /
Pumphrey, Edward Gary 40 Gold Coin Court Colorado Springs, CO 80919 / US | [1993/18] | Representative(s) | Schoppe, Fritz Schoppe, Zimmermann, Stöckeler & Zinkler Patentanwälte Postfach 246 82043 Pullach bei München / DE | [N/P] |
| Former [1993/18] | Schoppe, Fritz, Dipl.-Ing. Patentanwalt, Georg-Kalb-Strasse 9 D-82049 Pullach / DE | Application number, filing date | 92117853.9 | 19.10.1992 | [1993/18] | Priority number, date | US19910786695 | 01.11.1991 Original published format: US 786695 | US19910786459 | 01.11.1991 Original published format: US 786459 | US19910786690 | 01.11.1991 Original published format: US 786690 | US19910786633 | 01.11.1991 Original published format: US 786633 | US19910786447 | 01.11.1991 Original published format: US 786447 | [1993/18] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0539831 | Date: | 05.05.1993 | Language: | EN | [1993/18] | Type: | A3 Search report | No.: | EP0539831 | Date: | 26.04.1995 | Language: | EN | [1995/17] | Type: | B1 Patent specification | No.: | EP0539831 | Date: | 03.06.1998 | Language: | EN | [1998/23] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 10.03.1995 | Classification | IPC: | H03M1/66, G01R31/28, H03K5/13, H03K5/14 | [1995/17] | CPC: |
G01R31/2841 (EP);
G01R31/31922 (EP);
H03K5/131 (EP);
H03K5/133 (EP);
H03M1/687 (EP);
H03K2005/00097 (EP);
|
| Former IPC [1993/18] | H03M1/66, G01R31/28 | Designated contracting states | DE, FR, GB [1993/18] | Title | German: | Programmierbares Kapazitätsverzögerungselement in Pseudo-NMOS-Technik | [1993/18] | English: | Pseudo-NMOS programmable capacitance delay element | [1993/18] | French: | Elément à retard à capacitance programmable en pseudo-NMOS | [1993/18] | Miscellaneous | EPB 1998/23: (deleted) | EPB 1998/23: (deleted) | EPB 1998/23: (deleted) | EPB 1997/24: Teilanmeldung 97104641.2 eingereicht am 18/03/97 | EPB 1997/24: Divisional application 97104641.2 filed on 18/03/97 | EPB 1997/24: Demande divisionnaire 97104641.2 déposée le 18/03/97 | Examination procedure | 25.08.1995 | Examination requested [1995/42] | 18.12.1996 | Despatch of a communication from the examining division (Time limit: M04) | 26.03.1997 | Reply to a communication from the examining division | 05.08.1997 | Despatch of communication of intention to grant (Approval: No) | 18.11.1997 | Despatch of communication of intention to grant (Approval: later approval) | 02.12.1997 | Communication of intention to grant the patent | 08.01.1998 | Fee for grant paid | 08.01.1998 | Fee for publishing/printing paid | Divisional application(s) | EP97104641.2 / EP0793345 | Opposition(s) | 04.03.1999 | No opposition filed within time limit [1999/21] | Fees paid | Renewal fee | 19.09.1994 | Renewal fee patent year 03 | 25.09.1995 | Renewal fee patent year 04 | 16.09.1996 | Renewal fee patent year 05 | 26.09.1997 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]GB2045561 (ICL) [A] 1,2,4 * the whole document *; | [A]US4899071 (MORALES) [A] 1,5 * column 3, line 65 - column 4, line 64; figure 3 *; | [A]GB2213338 (ICL) [A] 1,2,4 * the whole document * | [A] - "Digital Programmable Clock Pulse Shaper", IBM TECHNICAL DISCLOSURE BULLETIN, (198409), vol. 27, no. 4B, pages 1 - 2 [A] 1 * the whole document * | [A] - LOUNG ET AL, "strobe pulse generator", IBM TECHNICAL DISCLOSURE BULLETIN, (198306), vol. 26, no. 1, pages 310 - 311 [A] 1 * the whole document * |