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EP0501561
European procedure
Extract from the Register of European Patents
EP About this file: EP0501561
| EP0501561 - Method of manufacturing a semiconductor device whereby a self-aligned cobalt or nickel silicide is formed [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 24.10.1997 Database last updated on 12.11.2024 | Most recent event Tooltip | 28.12.2002 | Lapse of the patent in a contracting state | published on 12.02.2003 [2003/07] | Applicant(s) | For all designated states Koninklijke Philips Electronics N.V. Groenewoudseweg 1 5621 BA Eindhoven / NL | [N/P] |
| Former [1992/36] | For all designated states Philips Electronics N.V. Groenewoudseweg 1 NL-5621 BA Eindhoven / NL | Inventor(s) | 01 /
Duchateau, Johan Philippe William c/o INT. OCTROOIBUREAU B.V., Prof. Holstlaan 6 NL-5656 AA Eindhoven / NL | 02 /
Reader, Alec Harold c/o INT. OCTROOIBUREAU B.V., Prof. Holstlaan 6 NL-5656 AA Eindhoven / NL | 03 /
van der Kolk, Gerrit Jan c/o INT. OCTROOIBUREAU B.V., Prof. Holstlaan 6 NL-5656 AA Eindhoven / NL | [1996/51] |
| Former [1992/36] | 01 /
Duchateau, John Philippe William c/o INT. OCTROOIBUREAU B.V., Prof. Holstlaan 6 NL-5656 AA Eindhoven / NL | ||
| 02 /
Reader, Alec Harold c/o INT. OCTROOIBUREAU B.V., Prof. Holstlaan 6 NL-5656 AA Eindhoven / NL | |||
| 03 /
van der Kolk, Gerrit Jan c/o INT. OCTROOIBUREAU B.V., Prof. Holstlaan 6 NL-5656 AA Eindhoven / NL | Representative(s) | Veerman, Jan Willem INTERNATIONAAL OCTROOIBUREAU B.V., Prof. Holstlaan 6 5656 AA Eindhoven / NL | [N/P] |
| Former [1992/36] | Veerman, Jan Willem INTERNATIONAAL OCTROOIBUREAU B.V., Prof. Holstlaan 6 NL-5656 AA Eindhoven / NL | Application number, filing date | 92200459.3 | 18.02.1992 | [1992/36] | Priority number, date | NL19910000334 | 26.02.1991 Original published format: NL 9100334 | [1992/36] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0501561 | Date: | 02.09.1992 | Language: | EN | [1992/36] | Type: | B1 Patent specification | No.: | EP0501561 | Date: | 18.12.1996 | Language: | EN | [1996/51] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 18.06.1992 | Classification | IPC: | H01L21/285, H01L21/768, H01L21/3205 | [1996/51] | CPC: |
H01L21/76897 (EP,US);
H01L21/28 (KR);
H01L21/28518 (EP,US);
H01L21/76889 (EP,US);
H01L29/665 (EP,US);
H01L29/7848 (EP,US);
|
| Former IPC [1992/36] | H01L21/285, H01L21/90, H01L21/3205 | Designated contracting states | DE, FR, GB, IT, NL [1992/36] | Title | German: | Verfahren zum Herstellen einer Halbleiteranordnung, wobei ein selbstregistrierendes Kobalt- oder Nickelsilizid gebildet wird | [1992/36] | English: | Method of manufacturing a semiconductor device whereby a self-aligned cobalt or nickel silicide is formed | [1992/36] | French: | Procédé de fabrication d'un dispositif semiconducteur consistant à former un siliciure de cobalt ou de nickel | [1996/51] |
| Former [1992/36] | Procédé de fabrication d'un dispositif semiconducteurs consistant à former un siliciure de cobalt ou de nickel | Examination procedure | 18.02.1993 | Examination requested [1993/16] | 16.02.1996 | Despatch of communication of intention to grant (Approval: Yes) | 21.06.1996 | Communication of intention to grant the patent | 01.10.1996 | Fee for grant paid | 01.10.1996 | Fee for publishing/printing paid | Opposition(s) | 19.09.1997 | No opposition filed within time limit [1997/50] | Fees paid | Renewal fee | 25.02.1994 | Renewal fee patent year 03 | 28.02.1995 | Renewal fee patent year 04 | 29.02.1996 | Renewal fee patent year 05 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | NL | 18.12.1996 | [2003/07] | Documents cited: | Search | [A]EP0349058 (PHILIPS NV [NL]) | [A] - IEEE TRANSACTIONS ON ELECTRON DEVICES. vol. 36, no. 11, November 1989, NEW YORK US pages 2440 - 2446; E.K. BROADBENT ET.AL.: 'application of self aligned CoSi2 interconnection in submicron CMOS transistors' |