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EP0497596
European procedure
Extract from the Register of European Patents
EP About this file: EP0497596
| EP0497596 - Method for fabricating integrated circuit structures [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 15.11.1996 Database last updated on 27.07.2024 | Most recent event Tooltip | 15.11.1996 | No opposition filed within time limit | published on 02.01.1997 [1997/01] | Applicant(s) | For all designated states STMicroelectronics, Inc. 1310 Electronics Drive Carrollton, TX 75006-5039 / US | [N/P] |
| Former [1992/32] | For all designated states SGS-THOMSON MICROELECTRONICS, INC. 1310 Electronics Drive Carrollton Texas 75006 / US | Inventor(s) | 01 /
Liou, Fu-Tai 2027 Lansdown Drive Carrollton, Texas 75010 / US | 02 /
Wei, Che-Chia 4313 Purdue Circle Plano, Texas 75093 / US | [1992/32] | Representative(s) | Palmer, Roger, et al PAGE, WHITE & FARRER 54 Doughty Street London WC1N 2LS / GB | [1992/32] | Application number, filing date | 92300795.9 | 30.01.1992 | [1992/32] | Priority number, date | US19910648650 | 31.01.1991 Original published format: US 648650 | [1992/32] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0497596 | Date: | 05.08.1992 | Language: | EN | [1992/32] | Type: | A3 Search report | No.: | EP0497596 | Date: | 28.10.1992 | Language: | EN | [1992/44] | Type: | B1 Patent specification | No.: | EP0497596 | Date: | 10.01.1996 | Language: | EN | [1996/02] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 07.09.1992 | Classification | IPC: | H01L21/3205, H01L21/28, H01L21/285 | [1992/44] | CPC: |
H01L21/28052 (EP,KR);
H01L21/28518 (EP,KR);
H01L29/665 (EP,KR)
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| Former IPC [1992/32] | H01L21/285 | Designated contracting states | DE, FR, GB, IT [1992/32] | Title | German: | Verfahren zum Herstellen von integrierten Schaltstrukturen | [1992/32] | English: | Method for fabricating integrated circuit structures | [1992/32] | French: | Procédé de fabrication des structures de circuit intégré | [1992/32] | Examination procedure | 16.04.1993 | Examination requested [1993/24] | 16.11.1993 | Despatch of a communication from the examining division (Time limit: M06) | 19.05.1994 | Reply to a communication from the examining division | 14.03.1995 | Despatch of communication of intention to grant (Approval: Yes) | 11.07.1995 | Communication of intention to grant the patent | 06.10.1995 | Fee for grant paid | 06.10.1995 | Fee for publishing/printing paid | Opposition(s) | 11.10.1996 | No opposition filed within time limit [1997/01] | Fees paid | Renewal fee | 20.12.1993 | Renewal fee patent year 03 | 16.01.1995 | Renewal fee patent year 04 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]US4470189 (ROBERTS STANLEY [US], et al); | [A]US4128670 (GAENSSLEN FRITZ H); | [A]EP0071029 (IBM [US]) | [A] - JOURNAL OF THE ELECTROCHEMICAL SOCIETY. vol. 133, no. 11, November 1986, MANCHESTER, NEW HAMPSHIRE US pages 2386 - 2389; M. LIN ET AL.: 'An Environment-Insensitive Trilayer Structure for Titanium Silicide Formation' | [A] - JAPANESE JOURNAL OF APPLIED PHYSICS, SUPPLEMENTS. vol. 20, 1981, TOKYO JA pages 49 - 54; S. SAITHO ET AL.: 'Formation of a Double-Hetero Si/CoSi2/Si Structure Using Molecular Beam and Solid Phase Epitaxies' Supplement 20-1 | [A] - IBM TECHNICAL DISCLOSURE BULLETIN. vol. 22, no. 2, July 1979, NEW YORK US pages 598 - 599; J.K. HOWARD: 'High Conductivity Transition Metal Silicide (NbSi2) for FET Gate Structures' | [A] - APPLIED PHYSICS LETTERS. vol. 50, no. 14, 6 April 1987, NEW YORK US pages 933 - 934; H.T.G. HENTZELL ET AL.: 'Formation of Aluminum Silicide between Two Layers of Amorphous Silicon' |