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EP0550163
European procedure
Extract from the Register of European Patents
EP About this file: EP0550163
| EP0550163 - Circuit architecture for supporting multiple-channel DMA operations [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 02.06.2000 Database last updated on 13.07.2024 | Most recent event Tooltip | 02.06.2000 | No opposition filed within time limit | published on 19.07.2000 [2000/29] | Applicant(s) | For all designated states SUN MICROSYSTEMS, INC. 2550 Garcia Avenue Mountain View, CA 94043 / US | [1993/27] | Inventor(s) | 01 /
Sodos, Martin 3535 Feller Avenue San Jose, California 95127 / US | [1993/27] | Representative(s) | Wombwell, Francis Forresters 15, Hamilton Square Birkenhead Merseyside CH41 6BR / GB | [N/P] |
| Former [1993/27] | Wombwell, Francis Potts, Kerr & Co. 15, Hamilton Square Birkenhead Merseyside L41 6BR / GB | Application number, filing date | 92311130.6 | 07.12.1992 | [1993/27] | Priority number, date | US19910814765 | 30.12.1991 Original published format: US 814765 | [1993/27] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0550163 | Date: | 07.07.1993 | Language: | EN | [1993/27] | Type: | B1 Patent specification | No.: | EP0550163 | Date: | 04.08.1999 | Language: | EN | [1999/31] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 20.04.1993 | Classification | IPC: | G06F13/28, G06F5/06 | [1993/27] | CPC: |
G06F13/28 (EP,KR,US);
G06F5/065 (EP,US)
| Designated contracting states | DE, FR, GB, IT [1993/27] | Title | German: | Schaltungsarchitektur zum mehrkanaligen DMA-Betrieb | [1993/27] | English: | Circuit architecture for supporting multiple-channel DMA operations | [1993/27] | French: | Architecture de circuit pour l'opération à canaux multiples d'accès direct en mémoire | [1993/27] | Examination procedure | 30.12.1993 | Examination requested [1994/09] | 19.12.1996 | Despatch of a communication from the examining division (Time limit: M04) | 22.04.1997 | Reply to a communication from the examining division | 16.10.1997 | Despatch of a communication from the examining division (Time limit: M04) | 16.02.1998 | Reply to a communication from the examining division | 31.08.1998 | Despatch of communication of intention to grant (Approval: Yes) | 21.01.1999 | Communication of intention to grant the patent | 17.04.1999 | Fee for grant paid | 17.04.1999 | Fee for publishing/printing paid | Opposition(s) | 05.05.2000 | No opposition filed within time limit [2000/29] | Fees paid | Renewal fee | 30.11.1994 | Renewal fee patent year 03 | 27.11.1995 | Renewal fee patent year 04 | 22.11.1996 | Renewal fee patent year 05 | 24.11.1997 | Renewal fee patent year 06 | 20.11.1998 | Renewal fee patent year 07 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [XP]EP0486145 (IBM [US]); | [Y]WO8400222 (ELXSI [US]); | [A]WO9111767 (AUSPEX SYSTEMS INC [US]); | [A]EP0432978 (IBM [US]) | [Y] - IBM TECHNICAL DISCLOSURE BULLETIN vol. 32, no. 8A, January 1990, NEW YORK US pages 418 - 421 'high speed buffer for n x 1 packet multiplexing' |