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EP0550255
European procedure
Extract from the Register of European Patents
EP About this file: EP0550255
| EP0550255 - Transistor spacer structure [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 15.01.1999 Database last updated on 28.03.2026 | Most recent event Tooltip | 15.01.1999 | No opposition filed within time limit | published on 03.03.1999 [1999/09] | Applicant(s) | For all designated states STMicroelectronics, Inc. 1310 Electronics Drive Carrollton, TX 75006-5039 / US | [1999/08] |
| Former [1993/27] | For all designated states SGS-THOMSON MICROELECTRONICS, INC. 1310 Electronics Drive Carrollton Texas 75006 / US | Inventor(s) | 01 /
Chen, Fusen E. 18175 Midway Road No.227 Dallas, Texas 75287 / US | 02 /
Bryant, Frank Randolph 2125 Crestwood Denton, Texas 76201 / US | 03 /
Dixit, Girish Anant 18175 Midway Road, No.159 Dallas, Texas 75287 / US | [1993/27] | Representative(s) | Palmer, Roger, et al PAGE, WHITE & FARRER 54 Doughty Street London WC1N 2LS / GB | [1993/27] | Application number, filing date | 92311751.9 | 23.12.1992 | [1993/27] | Priority number, date | US19910816627 | 31.12.1991 Original published format: US 816627 | [1993/27] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0550255 | Date: | 07.07.1993 | Language: | EN | [1993/27] | Type: | A3 Search report | No.: | EP0550255 | Date: | 25.08.1993 | Language: | EN | [1993/34] | Type: | B1 Patent specification | No.: | EP0550255 | Date: | 11.03.1998 | Language: | EN | [1998/11] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 05.07.1993 | Classification | IPC: | H01L21/336, H01L21/28 | [1993/27] | CPC: |
H10D30/0227 (EP,US);
H10D64/021 (EP,US);
H10P30/22 (EP,US)
| Designated contracting states | DE, FR, GB, IT [1993/27] | Title | German: | Seitenwand-Abstandsstruktur für Feldeffekttransistor | [1993/27] | English: | Transistor spacer structure | [1993/27] | French: | Structure de parois d'espacement pour transistor à effet de champ | [1993/27] | Examination procedure | 27.01.1994 | Examination requested [1994/13] | 07.03.1994 | Despatch of a communication from the examining division (Time limit: M06) | 21.10.1994 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time | 03.12.1994 | Reply to a communication from the examining division | 13.11.1995 | Despatch of a communication from the examining division (Time limit: M04) | 07.03.1996 | Reply to a communication from the examining division | 28.04.1997 | Despatch of communication of intention to grant (Approval: Yes) | 18.06.1997 | Communication of intention to grant the patent | 23.08.1997 | Fee for grant paid | 23.08.1997 | Fee for publishing/printing paid | Opposition(s) | 12.12.1998 | No opposition filed within time limit [1999/09] | Request for further processing for: | 03.12.1994 | Request for further processing filed | 03.12.1994 | Full payment received (date of receipt of payment) Request granted | 20.12.1994 | Decision despatched | Fees paid | Renewal fee | 10.12.1994 | Renewal fee patent year 03 | 21.12.1995 | Renewal fee patent year 04 | 13.12.1996 | Renewal fee patent year 05 | 22.12.1997 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X] IBM TECHNICAL DISCLOSURE BULLETIN. vol. 26, no. 3B, August 1983, NEW YORK US pages 1316 - 1317 J.M. BLUM ET AL. 'SIDEWALL OXIDE STRUCTURE AND METHOD FOR POLYSILICON GATE DEVICES TO MINIMIZE CONSUMPTION OF FIELD OXIDE' [X] | [X] IBM TECHNICAL DISCLOSURE BULLETIN. vol. 24, no. 2, July 1981, NEW YORK US pages 1293 - 1295 P.J. TSANG 'Method to improve the controllability of lightly doped drain SiO2 spacer formation' [X] | [X] IEEE ELECTRON DEVICE LETTERS. vol. 10, no. 11, November 1989, NEW YORK US pages 487 - 489 CHIH-YUAN LU ET AL. 'Submicrometer salicide CMOS devices with self-aligned shallow/deep junctions' [X] | [A] IBM TECHNICAL DISCLOSURE BULLETIN. vol. 32, no. 8A, January 1990, NEW YORK US pages 312 - 313 'Method to minimize junction capacitance added by a punch-through (halo) implant' [A] |