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EP0576774
European procedure
Extract from the Register of European Patents
EP About this file: EP0576774
| EP0576774 - Voltage regulator for memory devices [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 14.07.2000 Database last updated on 31.08.2024 | Most recent event Tooltip | 14.07.2000 | No opposition filed within time limit | published on 30.08.2000 [2000/35] | Applicant(s) | For all designated states STMicroelectronics Srl Via C. Olivetti, 2 20041 Agrate Brianza (Milano) / IT | [N/P] |
| Former [1998/35] | For all designated states STMicroelectronics S.r.l. Via C. Olivetti, 2 20041 Agrate Brianza (Milano) / IT | ||
| Former [1994/01] | For all designated states SGS-THOMSON MICROELECTRONICS S.r.l. Via C. Olivetti, 2 I-20041 Agrate Brianza (Milano) / IT | Inventor(s) | 01 /
Flocchi, Carlo Via G. Pascoli I-27100 Belgioioso (PV) / IT | 02 /
Torelli, Guido Via Cadorna, 4 I-27016 S. Alessio (PV) / IT | [1994/01] | Representative(s) | Botti, Mario Botti & Ferrari S.p.A. Via Cappellini, 11 20124 Milano / IT | [N/P] |
| Former [1999/17] | Botti, Mario Botti & Ferrari S.r.l. Via Locatelli, 5 20124 Milano / IT | Application number, filing date | 92830340.3 | 30.06.1992 | [1994/01] | Filing language | IT | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0576774 | Date: | 05.01.1994 | Language: | EN | [1994/01] | Type: | B1 Patent specification | No.: | EP0576774 | Date: | 15.09.1999 | Language: | EN | [1999/37] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 19.03.1993 | Classification | IPC: | G11C16/06 | [1994/01] | CPC: |
G11C16/30 (EP,US)
| Designated contracting states | DE, FR, GB, IT [1994/01] | Title | German: | Spannungsregler für Speichergeräte | [1994/01] | English: | Voltage regulator for memory devices | [1994/01] | French: | Régulateur de tension pour dispositifs de mémoire | [1994/01] | Examination procedure | 27.05.1994 | Examination requested [1994/35] | 20.12.1996 | Despatch of a communication from the examining division (Time limit: M06) | 27.06.1997 | Reply to a communication from the examining division | 20.03.1998 | Despatch of a communication from the examining division (Time limit: M06) | 30.09.1998 | Reply to a communication from the examining division | 12.11.1998 | Despatch of communication of intention to grant (Approval: Yes) | 22.03.1999 | Communication of intention to grant the patent | 16.06.1999 | Fee for grant paid | 16.06.1999 | Fee for publishing/printing paid | Opposition(s) | 16.06.2000 | No opposition filed within time limit [2000/35] | Fees paid | Renewal fee | 21.06.1994 | Renewal fee patent year 03 | 21.06.1995 | Renewal fee patent year 04 | 24.06.1996 | Renewal fee patent year 05 | 20.06.1997 | Renewal fee patent year 06 | 19.06.1998 | Renewal fee patent year 07 | 24.06.1999 | Renewal fee patent year 08 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]US5086238 (WATANABE TAKAO [JP], et al); | [A]GB2214380 (INTEL CORP [US]) | [A] - 1990 SYMPOSIUM ON VLSI CIRCUITS June 1990, HONOLULU, US pages 99 - 100 SHOHJI ET AL 'A novel automatic erase technique using an internal voltage generator for 1 Mbit flash EEPROM' |