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Extract from the Register of European Patents

EP About this file: EP0547216

EP0547216 - RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING MULTIPLE TYPED REGISTER SETS [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  28.07.2000
Database last updated on 18.10.2024
Most recent event   Tooltip07.12.2007Lapse of the patent in a contracting state
New state(s): IT
published on 09.01.2008  [2008/02]
Applicant(s)For all designated states
Seiko Epson Corporation
11F, NS Building 4-1, 2-Chome Nishishinjuku Shinjuku-ku
Tokyo 163-08 / JP
[N/P]
Former [1999/39]For all designated states
SEIKO EPSON CORPORATION
11F, NS Building 4-1, 2-Chome Nishishinjuku Shinjuku-ku
Tokyo 163-08 / JP
Former [1995/14]For all designated states
SEIKO EPSON CORPORATION
11F, NS Building 4-1, 2-Chome Nishishinjuku Shinjuku-ku
Tokyo 163-08 / JP
Former [1993/25]For all designated states
S-MOS SYSTEMS, INC.
2460 North First Street
San Jose, CA 95131-1002 / US
Inventor(s)01 / GARG, Sanjiv
46820 Sentinel Drive
Fremont, CA 94539 / US
02 / LENTZ, Derek, J.
17400 Phillips Avenue
Los Gatos, CA 95032 / US
03 / NGUYEN, Le Trong
15096 Danielle Place
Monte Sereno, CA 95030 / US
04 / CHEN, Sho, Long
14411 Quito Road
Saratoga, CA 95070 / US
[1993/25]
Representative(s)Grünecker Patent- und Rechtsanwälte PartG mbB
Leopoldstraße 4
80802 München / DE
[N/P]
Former [1993/25]Grünecker, Kinkeldey, Stockmair & Schwanhäusser Anwaltssozietät
Maximilianstrasse 58
D-80538 München / DE
Application number, filing date92915765.908.07.1992
[1993/25]
WO1992US05720
Priority number, dateUS1991072677308.07.1991         Original published format: US 726773
[1993/25]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report
No.:WO9301543
Date:21.01.1993
Language:EN
[1993/03]
Type: A1 Application with search report 
No.:EP0547216
Date:23.06.1993
Language:EN
The application published by WIPO in one of the EPO official languages on 21.01.1993 takes the place of the publication of the European patent application.
[1993/25]
Type: B1 Patent specification 
No.:EP0547216
Date:29.09.1999
Language:EN
[1999/39]
Search report(s)International search report - published on:EP21.01.1993
ClassificationIPC:G06F9/30
[1993/25]
CPC:
G06F9/30029 (EP,US); G06F9/30 (KR); G06F9/30036 (EP,KR,US);
G06F9/30112 (EP,US); G06F9/30116 (EP,US); G06F9/3012 (EP,US);
G06F9/30123 (EP,US); G06F9/3013 (EP,US); G06F9/30138 (EP,US);
G06F9/30167 (EP,US); G06F9/30189 (EP,US); G06F9/3851 (EP,KR,US) (-)
Designated contracting statesAT,   BE,   CH,   DE,   DK,   ES,   FR,   GB,   GR,   IT,   LI,   LU,   MC,   NL,   SE [1993/25]
TitleGerman:RISC MIKROPROZESSORARCHITEKTUR MIT MEHRERE REGISTERSÄTZE VON UNTERSCHIEDLICHEN TYPEN[1993/25]
English:RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING MULTIPLE TYPED REGISTER SETS[1993/25]
French:ARCHITECTURE DE MICROPROCESSEUR RISC METTANT EN OEUVRE DIVERS ENSEMBLES DE TYPES DE REGISTRES[1998/36]
Former [1993/25]ARCHITECTURE DE MICROPROCESSEUR RISC METTANT EN OEUVRE DIVERS ENSEMBLES DE REGISTRES TYPES
Entry into regional phase24.02.1993National basic fee paid 
24.02.1993Designation fee(s) paid 
20.07.1993Examination fee paid 
Examination procedure20.07.1993Examination requested  [1993/37]
14.04.1997Despatch of a communication from the examining division (Time limit: M04)
22.08.1997Reply to a communication from the examining division
06.11.1997Despatch of a communication from the examining division (Time limit: M04)
11.03.1998Reply to a communication from the examining division
27.07.1998Despatch of communication of intention to grant (Approval: Yes)
22.02.1999Communication of intention to grant the patent
28.05.1999Fee for grant paid
28.05.1999Fee for publishing/printing paid
Divisional application(s)EP99102406.8  / EP0911724
Opposition(s)30.06.2000No opposition filed within time limit [2000/37]
Fees paidRenewal fee
29.07.1994Renewal fee patent year 03
31.07.1995Renewal fee patent year 04
31.07.1996Renewal fee patent year 05
30.07.1997Renewal fee patent year 06
29.07.1998Renewal fee patent year 07
29.07.1999Renewal fee patent year 08
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipAT29.09.1999
BE29.09.1999
CH29.09.1999
ES29.09.1999
GR29.09.1999
IT29.09.1999
LI29.09.1999
NL29.09.1999
SE29.09.1999
DK29.12.1999
[2008/02]
Former [2004/07]AT29.09.1999
BE29.09.1999
CH29.09.1999
ES29.09.1999
GR29.09.1999
LI29.09.1999
NL29.09.1999
SE29.09.1999
DK29.12.1999
Former [2003/45]AT29.09.1999
BE29.09.1999
CH29.09.1999
ES29.09.1999
LI29.09.1999
NL29.09.1999
SE29.09.1999
DK29.12.1999
Former [2003/07]AT29.09.1999
BE29.09.1999
CH29.09.1999
ES29.09.1999
LI29.09.1999
NL29.09.1999
SE29.09.1999
Former [2002/25]AT29.09.1999
BE29.09.1999
CH29.09.1999
ES29.09.1999
LI29.09.1999
SE29.09.1999
Former [2002/23]AT29.09.1999
BE29.09.1999
CH29.09.1999
LI29.09.1999
SE29.09.1999
Former [2000/52]AT29.09.1999
BE29.09.1999
CH29.09.1999
LI29.09.1999
Former [2000/50]AT29.09.1999
BE29.09.1999
CH03.01.2000
LI03.01.2000
Former [2000/24]AT29.09.1999
BE29.09.1999
Cited inInternational search[X]US4212076  (CONNERS JOHN P [US]);
 [X]EP0170284  (NEC CORP [JP]);
 [X]EP0213843  (ADVANCED MICRO DEVICES INC [US]);
 [X]GB2190521  (INTEL CORP);
 [XP]EP0454636  (ST MICROELECTRONICS SRL [IT])
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.