EP0584778 - Method of preparing a semiconductor substrate [Right-click to bookmark this link] | |||
Former [1994/09] | Semiconductor substrate and method for preparing it | ||
[2003/13] | Status | No opposition filed within time limit Status updated on 10.09.2004 Database last updated on 20.09.2024 | Most recent event Tooltip | 28.12.2007 | Lapse of the patent in a contracting state New state(s): IT | published on 30.01.2008 [2008/05] | Applicant(s) | For all designated states CANON KABUSHIKI KAISHA 30-2, 3-chome, Shimomaruko, Ohta-ku Tokyo / JP | [N/P] |
Former [1994/09] | For all designated states CANON KABUSHIKI KAISHA 30-2, 3-chome, Shimomaruko, Ohta-ku Tokyo / JP | Inventor(s) | 01 /
Yonehara, Takao, c/o Canon Kabushiki Kaisha 3-30-2, Shimomaruko Ohta-ku, Tokyo 146 / JP | [1994/09] | Representative(s) | Leson, Thomas Johannes Alois, et al TBK Bavariaring 4-6 80336 München / DE | [N/P] |
Former [2002/38] | Leson, Thomas Johannes Alois, Dipl.-Ing., et al c/o TBK-Patent, P.O. Box 20 19 18 80019 München / DE | ||
Former [1994/09] | Tiedtke, Harro, Dipl.-Ing. Patentanwaltsbüro Tiedtke-Bühling-Kinne & Partner Bavariaring 4 D-80336 München / DE | Application number, filing date | 93113473.8 | 24.08.1993 | [1994/09] | Priority number, date | JP19920247173 | 25.08.1992 Original published format: JP 24717392 | [1994/09] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0584778 | Date: | 02.03.1994 | Language: | EN | [1994/09] | Type: | A3 Search report | No.: | EP0584778 | Date: | 08.10.1997 | [1997/41] | Type: | B1 Patent specification | No.: | EP0584778 | Date: | 05.11.2003 | Language: | EN | [2003/45] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 21.08.1997 | Classification | IPC: | H01L21/20, H01L21/76 | [1994/09] | CPC: |
H01L21/2007 (EP,US);
H01L2224/83894 (EP,US);
Y10S148/012 (EP);
Y10S148/135 (EP)
| Designated contracting states | DE, FR, GB, IT, NL [1994/09] | Title | German: | Verfahren zur Herstellung eines Halbleitersubstrats | [2003/13] | English: | Method of preparing a semiconductor substrate | [2003/13] | French: | Procédé de fabrication d'un substrat semiconducteur | [2003/13] |
Former [1994/09] | Halbleitersubstrat und Verfahren zu seiner Herstellung | ||
Former [1994/09] | Semiconductor substrate and method for preparing it | ||
Former [1994/09] | Substrat semi-conducteur et procédé de sa fabrication | Examination procedure | 23.02.1998 | Examination requested [1998/17] | 17.02.1999 | Despatch of a communication from the examining division (Time limit: M06) | 12.08.1999 | Reply to a communication from the examining division | 17.02.2000 | Despatch of a communication from the examining division (Time limit: M04) | 14.06.2000 | Reply to a communication from the examining division | 01.02.2001 | Despatch of a communication from the examining division (Time limit: M06) | 09.08.2001 | Reply to a communication from the examining division | 19.03.2003 | Communication of intention to grant the patent | 21.07.2003 | Fee for grant paid | 21.07.2003 | Fee for publishing/printing paid | Opposition(s) | 06.08.2004 | No opposition filed within time limit [2004/44] | Fees paid | Renewal fee | 29.08.1995 | Renewal fee patent year 03 | 27.08.1996 | Renewal fee patent year 04 | 27.08.1997 | Renewal fee patent year 05 | 28.08.1998 | Renewal fee patent year 06 | 31.08.1999 | Renewal fee patent year 07 | 30.08.2000 | Renewal fee patent year 08 | 29.08.2001 | Renewal fee patent year 09 | 29.08.2002 | Renewal fee patent year 10 | 28.08.2003 | Renewal fee patent year 11 |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | IT | 05.11.2003 | NL | 05.11.2003 | [2008/05] |
Former [2004/33] | NL | 05.11.2003 | Documents cited: | Search | [A]US4774196 (BLANCHARD RICHARD A [US]) [A] 1,2 * claims 1,3,15 *; | [A]DE3829906 (SIEMENS AG [DE]) [A] 1,2 * claims 1,2 *; | [A] - GOETZ G G ET AL, Generalized bonding, 1989, NEW YORK, NY, USA, IEEE, USA, PAGE(S) 125 - 126, 1989 IEEE SOS/SOI TECHNOLOGY CONFERENCE (CAT. NO.89CH2796-1), STATELINE, NV, USA, 3-5 OCT. 1989, XP000167660 [A] 1,2,6 * the whole document * | [A] - Y. SUGAWARA ET AL., "NEW DIELECTRIC ISOLATION FOR HIGH VOLTAGE POWER ICS BY SINGLE SILICON POLY SILICON DIRECT BONDING (SPDB) TECHNIQUE", PROCEEDINGS OF TGHE 1992 INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES&IC'S., TOKYO, pages 316 - 321, XP000340051 [A] 1,2,6 * the whole document * |