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Extract from the Register of European Patents

EP About this file: EP0590635

EP0590635 - A method for producing a multi-layered printed wiring board [Right-click to bookmark this link]
Former [1994/14]A plating method, a method for producing a multi-layered printed wiring board using the same, and the multi-layered printed wiring board
[1996/29]
StatusNo opposition filed within time limit
Status updated on  23.05.1997
Database last updated on 06.07.2024
Most recent event   Tooltip17.10.2008Change - applicantpublished on 19.11.2008  [2008/47]
Applicant(s)For all designated states
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
1006, Oaza Kadoma Kadoma-shi Osaka
571-8501 / JP
[2008/47]
Former [1994/14]For all designated states
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
1006, Ohaza Kadoma
Kadoma-shi, Osaka 571 / JP
Inventor(s)01 / Nakamura, Tsuneshi
11-24-48, Korigaoka
Hirakata-shi, Osaka / JP
[1994/14]
Representative(s)SSM Sandmair
Patentanwälte Rechtsanwalt
Partnerschaft mbB
Joseph-Wild-Straße 20
81829 München / DE
[N/P]
Former [1994/14]Schwabe - Sandmair - Marx
Stuntzstrasse 16
D-81677 München / DE
Application number, filing date93115712.729.09.1993
[1994/14]
Priority number, dateJP1992025954829.09.1992         Original published format: JP 25954892
[1994/14]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP0590635
Date:06.04.1994
Language:EN
[1994/14]
Type: B1 Patent specification 
No.:EP0590635
Date:17.07.1996
Language:EN
[1996/29]
Search report(s)(Supplementary) European search report - dispatched on:EP04.02.1994
ClassificationIPC:C23C18/22, H05K3/38, H05K3/46
[1994/14]
CPC:
C23C18/22 (EP); H05K3/381 (EP); H05K3/4661 (EP);
H05K1/16 (EP); H05K1/167 (EP); H05K2201/0209 (EP);
H05K2201/09509 (EP); H05K2203/025 (EP); H05K2203/0285 (EP);
H05K2203/0773 (EP); H05K3/0094 (EP); H05K3/426 (EP);
H05K3/4602 (EP) (-)
Designated contracting statesDE,   GB [1994/14]
TitleGerman:Verfahren zur Herstellung einer mehrschichtigen Leiterplatte[1996/29]
English:A method for producing a multi-layered printed wiring board[1996/29]
French:Procédé pour la fabrication d'une plaque à circuit imprimé multicouche[1996/29]
Former [1994/14]Plattierungsverfahren, Verfahren zur Herstellung einer mehrschichtigen Leiterplatte unter Verwendung desselben, und die mehrschichtige Leiterplatte
Former [1994/14]A plating method, a method for producing a multi-layered printed wiring board using the same, and the multi-layered printed wiring board
Former [1994/14]Procédé de plaquage, procédé pour la fabrication d'une plaque à circuit imprimé multicouche en l'utilisant, et la plaque à circuit imprimé multicouche
Examination procedure29.09.1993Examination requested  [1994/14]
06.02.1995Despatch of a communication from the examining division (Time limit: M05)
29.06.1995Reply to a communication from the examining division
28.07.1995Despatch of a communication from the examining division (Time limit: M04)
14.09.1995Reply to a communication from the examining division
30.10.1995Despatch of communication of intention to grant (Approval: Yes)
18.01.1996Communication of intention to grant the patent
01.04.1996Fee for grant paid
01.04.1996Fee for publishing/printing paid
Opposition(s)18.04.1997No opposition filed within time limit [1997/28]
Fees paidRenewal fee
30.08.1995Renewal fee patent year 03
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[XY]GB1276527  (INTERNATIONAL ELECTRONIC RESEARCH CORPORATION) [X] 1,4,6 * page 3, line 93 - page 4, line 14; figures 3-6 * [Y] 7,8,10,12,13,16-18,21-24;
 [Y]EP0478313  (INTERNATIONAL BUSINESS MACHINES CORPORATION) [Y] 7,8,10,12,13,24 * figure 2; claims 8,10 *;
 [D]JPH04148590  (...);
 [Y]EP0379686  (NIPPON CMK CORPORATION) [Y] 16-18,21-23 * the whole document *;
 [X]JPS52123334  ;
 [A]EP0197323  (BAYER AG) [A] 1,2,6,7,12,15,24,25 * column 2, line 20 - line 43 * * column 3, line 18 - line 20 * * column 5, line 6 - line 15 * * column 8, line 33 - line 35 *;
 [A]FR2227109  (CANON KABUSHIKI KAISHA) [A] 1,3,9,20 * page 5, line 3 - line 9 *;
 [A]DE3913966  (IBIDEN CO.) [A] 7,12,13,24,25 * figure -; claim 14 *
 [XA]  - A.F. BOGENSCHÜTZ ET AL., "Vergleichende Untersuchungen an verschiedenen Vorbehandlungsmethoden für unkaschierte Leiterplatten-Basismaterialien", GALVANOTECHNIK, SAULGAU/WURTT DE, (198303), vol. 74, no. 3, pages 269 - 274 [X] 1,2 * page 270: 2. Mechanische Aufrauhung * [A] 8,19
 [X]  - DATABASE WPI, 0, Derwent World Patents Index, vol. 77, no. 47, Database accession no. 77-83991Y, & JPS52123334 A 19771017 (DAINI SEIKOSHA) [X] 1 * abstract *
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.