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EP0606650
European procedure
Extract from the Register of European Patents
EP About this file: EP0606650
| EP0606650 - Nonvolatile semiconductor memory device [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 07.04.2000 Database last updated on 16.09.2024 | Most recent event Tooltip | 07.04.2000 | No opposition filed within time limit | published on 24.05.2000 [2000/21] | Applicant(s) | For all designated states Kabushiki Kaisha Toshiba 72, Horikawa-cho, Saiwai-ku Kawasaki-shi Kanagawa-ken 210-8572 / JP | [N/P] |
| Former [1999/22] | For all designated states KABUSHIKI KAISHA TOSHIBA 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210-8572 / JP | ||
| Former [1995/01] | For all designated states KABUSHIKI KAISHA TOSHIBA 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210, Tokyo / JP | ||
| Former [1994/29] | For all designated states Kabushiki Kaisha Toshiba 72, Horikawa-cho Saiwai-ku Kawasaki-shi / JP | Inventor(s) | 01 /
Atsumi, Shigeru, c/o Intellectual Property Div. K.K. TOSHIBA, 1-1 Shibaura 1-chome Minato-ku, Tokyo 105 / JP | 02 /
Banba, Hironori, c/o Intellectual Property Div. K.K. TOSHIBA, 1-1 Shibaura 1-chome Minato-ku, Tokyo 105 / JP | [1994/29] | Representative(s) | Lehn, Werner, et al Hoffmann Eitle, Patent- und Rechtsanwälte, Arabellastrasse 4 81925 München / DE | [N/P] |
| Former [1994/29] | Lehn, Werner, Dipl.-Ing., et al Hoffmann, Eitle & Partner, Patentanwälte, Arabellastrasse 4 D-81925 München / DE | Application number, filing date | 93121084.3 | 29.12.1993 | [1994/29] | Priority number, date | JP19930004305 | 13.01.1993 Original published format: JP 430593 | [1994/29] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0606650 | Date: | 20.07.1994 | Language: | EN | [1994/29] | Type: | A3 Search report | No.: | EP0606650 | Date: | 27.09.1995 | Language: | EN | [1995/39] | Type: | B1 Patent specification | No.: | EP0606650 | Date: | 02.06.1999 | Language: | EN | [1999/22] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 09.08.1995 | Classification | IPC: | G11C16/06 | [1994/29] | CPC: |
G11C16/08 (EP,KR,US);
G11C16/16 (EP,KR,US)
| Designated contracting states | DE, FR [1999/15] |
| Former [1994/29] | DE, FR, GB | Title | German: | Nichtflüchtige Halbleiterspeicheranordnung | [1994/29] | English: | Nonvolatile semiconductor memory device | [1994/29] | French: | Dispositif de mémoire non-volatile à semi-conducteur | [1994/29] | Examination procedure | 29.12.1993 | Examination requested [1994/29] | 07.07.1997 | Despatch of a communication from the examining division (Time limit: M06) | 19.01.1998 | Reply to a communication from the examining division | 22.07.1998 | Despatch of communication of intention to grant (Approval: Yes) | 27.11.1998 | Communication of intention to grant the patent | 17.02.1999 | Fee for grant paid | 17.02.1999 | Fee for publishing/printing paid | Opposition(s) | 03.03.2000 | No opposition filed within time limit [2000/21] | Fees paid | Renewal fee | 08.12.1995 | Renewal fee patent year 03 | 11.12.1996 | Renewal fee patent year 04 | 12.12.1997 | Renewal fee patent year 05 | 11.12.1998 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [PX]EP0525678 (TOSHIBA KK [JP]) [PX] 1,2 * column 5, line 39 - column 12, line 35; figures 1-6 *; | [PXA]EP0550751 (TOSHIBA KK [JP]) [PX] 1 * page 14, line 41 - page 15, line 43; figures 21-25; table 5 * [A] 13,17; | [E]US5295106 (JINBO TOSHIKATSU [JP]) [E] 1 * column 6, line 51 - column 12, line 32; figures 5-9 *; | [A]US4642798 (RAO KAMESWARA K [US]) | [A] - NAKAYAMA ET AL, "A new decoding scheme and erase sequence for 5V only sector erasable flash memory", SYMPOSIUM ON VLSI CIRCUITS, SEATTLE, US, (19920604), doi:doi:10.1109/VLSIC.1992.229255, pages 22 - 23, XP010064961 [A] 1,2 * page 22, column L, line 41 - column R, line 13; figure 3; table 1 * DOI: http://dx.doi.org/10.1109/VLSIC.1992.229255 | [A] - UMEZAWA ET AL, "A 5V-only operation 0.6um flashEEPROM with row decoder scheme in triple-well structure", IEEE JOURNAL OF SOLID-STATE CIRCUITS, NEW YORK US, vol. 27, no. 11, doi:doi:10.1109/4.165334, pages 1540 - 1545, XP000320440 [A] 1 * figure 3 * DOI: http://dx.doi.org/10.1109/4.165334 | by applicant | EP0550751 | US4642798 | - H. KUME ET AL., "A 3.42 pm2 Flash Memory Cell Technology Conformable to a Sector Erase", SYMPOSIUM ON VLSI TECHNOLOGY, (1991), pages 77 - 78, XP000259983 |