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EP0573241
European procedure
Extract from the Register of European Patents
EP About this file: EP0573241
| EP0573241 - Semiconductor devices with a double layered silicide structure and process of making it [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 08.12.2000 Database last updated on 10.05.2025 | Most recent event Tooltip | 08.12.2000 | No opposition filed within time limit | published on 24.01.2001 [2001/04] | Applicant(s) | For all designated states Samsung Electronics Co., Ltd. 416, Maetan-dong Paldal-gu Suwon-City, Kyungki-do / KR | [N/P] |
| Former [2000/05] | For all designated states SAMSUNG ELECTRONICS CO., LTD. 416, Maetan-dong, Paldal-gu Suwon-City, Kyungki-do / KR | ||
| Former [1993/49] | For all designated states SAMSUNG ELECTRONICS CO., LTD. 416 Maetan-3 Dong, Paldal-ku Suwon-city, Kyungki-do 441-373 / KR | Inventor(s) | 01 /
Paek, Su-Hyon Kaenari APT. 34-302, Yeoksam 2-dong Kangnam-gu, Seoul / KR | 02 /
Choi, Jin-Seog Samsung 1cha APT, 3-909, Maetan 2-dong Paldal-gu, Suwon-city, Kyungki-do / KR | [1993/49] | Representative(s) | Stanley, David William, et al DIBB LUPTON BROOMHEAD 117 The Headrow Leeds LS1 5JX / GB | [N/P] |
| Former [1994/45] | Stanley, David William, et al DIBB LUPTON BROOMHEAD 117 The Headrow, Leeds LS1 5JX / GB | ||
| Former [1993/49] | Stanley, David William APPLEYARD LEES & CO. 15 Clare Road Halifax West Yorkshire HX1 2HY / GB | Application number, filing date | 93304216.0 | 01.06.1993 | [1993/49] | Priority number, date | KR19940001492 | 30.05.1992 Original published format: KR 941492 | [1993/49] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0573241 | Date: | 08.12.1993 | Language: | EN | [1993/49] | Type: | A3 Search report | No.: | EP0573241 | Date: | 16.02.1994 | Language: | EN | [1994/07] | Type: | B1 Patent specification | No.: | EP0573241 | Date: | 09.02.2000 | Language: | EN | [2000/06] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 28.12.1993 | Classification | IPC: | H01L21/768, H01L23/485, H01L21/3205 | [1999/23] | CPC: |
H01L23/53271 (EP,US);
H01L21/324 (KR);
H01L21/76889 (EP,US);
H01L23/532 (EP,US);
H01L2924/0002 (EP,US)
| C-Set: |
H01L2924/0002, H01L2924/00 (EP,US)
|
| Former IPC [1994/07] | H01L21/90, H01L23/485, H01L21/3205 | ||
| Former IPC [1993/49] | H01L21/90, H01L23/485 | Designated contracting states | FR, GB, IT [1993/49] | Title | German: | Halbleitervorrichtungen mit einer doppelschichtigen Silizidstruktur und Verfahren zu ihrer Herstellung | [1993/49] | English: | Semiconductor devices with a double layered silicide structure and process of making it | [1993/49] | French: | Dispositifs semi-conducteurs comportant une structure à double couche de siliciure et leur procédé de fabrication | [1993/49] | Examination procedure | 29.07.1994 | Examination requested [1994/39] | 16.10.1996 | Despatch of a communication from the examining division (Time limit: M04) | 07.02.1997 | Reply to a communication from the examining division | 17.07.1997 | Despatch of a communication from the examining division (Time limit: M04) | 14.11.1997 | Reply to a communication from the examining division | 29.05.1998 | Despatch of a communication from the examining division (Time limit: M04) | 23.09.1998 | Reply to a communication from the examining division | 18.05.1999 | Despatch of communication of intention to grant (Approval: Yes) | 23.07.1999 | Communication of intention to grant the patent | 24.09.1999 | Fee for grant paid | 24.09.1999 | Fee for publishing/printing paid | Opposition(s) | 10.11.2000 | No opposition filed within time limit [2001/04] | Fees paid | Renewal fee | 26.06.1995 | Renewal fee patent year 03 | 02.07.1996 | Renewal fee patent year 04 | 26.06.1997 | Renewal fee patent year 05 | 01.06.1998 | Renewal fee patent year 06 | 12.05.1999 | Renewal fee patent year 07 | Penalty fee | Additional fee for renewal fee | 01.07.1996 | 04 M06 Fee paid on 02.07.1996 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]EP0295367 (IBM [US]) [A] 1-3,12 * column 1, line 34 - column 2, line 11 * * claims 1-3 * | [A] - K.W.CHOI ET AL., "IMPROVED SALICIDE PROCESS WITH MULTILAYER SILICIDE FORMATION", IBM TECHNICAL DISCLOSURE BULLETIN., NEW YORK US, (198412), vol. 27, no. 7B, pages 4402 - 4404 [A] 1-5,7,12 * page 4403, paragraph 2 * * figure 4B * | [A] - "UNDERLAYER FIR POLYCIDE PROCESS", IBM TECHNICAL DISCLOSURE BULLETIN., NEW YORK US, (198602), vol. 28, no. 9, pages 3968 - 3969 | [A] - "IMPROVED TISI2 FILMS FOR VLSI TECHNOLOGY", RESEARCH DISCLOSURE, HAVANT GB, (199103), vol. 323, page 208 |