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EP0643484
European procedure
Extract from the Register of European Patents
EP About this file: EP0643484
| EP0643484 - Offset reduction in a zero-detecting circuit [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 02.07.1999 Database last updated on 25.09.2024 | Most recent event Tooltip | 02.07.1999 | No opposition filed within time limit | published on 18.08.1999 [1999/33] | Applicant(s) | For all designated states STMicroelectronics Srl Via C. Olivetti, 2 20041 Agrate Brianza (Milano) / IT | [N/P] |
| Former [1998/35] | For all designated states STMicroelectronics S.r.l. Via C. Olivetti, 2 20041 Agrate Brianza (Milano) / IT | ||
| Former [1995/11] | For all designated states SGS-THOMSON MICROELECTRONICS S.r.l. Via C. Olivetti, 2 I-20041 Agrate Brianza (Milano) / IT | Inventor(s) | 01 /
Betti, Giorgio Viale Premuda 24 I-20129 Milano / IT | 02 /
Gadducci, Paolo Via delle Orchidee 28 I-56018 Tirrenia / IT | 03 /
Moloney David Via Brera 24 I-20010 Cornaredo / IT | [1995/11] | Representative(s) | Pellegri, Alberto, et al Società Italiana Brevetti S.p.A. Via Carducci, 8 20123 Milano / IT | [N/P] |
| Former [1995/11] | Pellegri, Alberto, et al c/o Società Italiana Brevetti S.p.A. Via Puccini, 7 I-21100 Varese / IT | Application number, filing date | 93830379.9 | 14.09.1993 | [1995/11] | Filing language | IT | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0643484 | Date: | 15.03.1995 | Language: | EN | [1995/11] | Type: | B1 Patent specification | No.: | EP0643484 | Date: | 26.08.1998 | Language: | EN | [1998/35] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 24.02.1994 | Classification | IPC: | H03K5/1536, H03F1/30 | [1995/11] | CPC: |
H03F1/303 (EP,US);
H03F3/45968 (EP,US);
H03K5/1536 (EP,US);
H03F2200/81 (EP,US)
| Designated contracting states | DE, FR, GB, IT [1995/11] | Title | German: | Offset-Verminderung in einer Nulldetektorschaltung | [1995/11] | English: | Offset reduction in a zero-detecting circuit | [1995/11] | French: | Réduction de décalage dans un circuit à détection de zéro | [1995/11] | Examination procedure | 18.03.1995 | Examination requested [1995/22] | 17.02.1997 | Despatch of a communication from the examining division (Time limit: M04) | 17.05.1997 | Reply to a communication from the examining division | 17.11.1997 | Despatch of communication of intention to grant (Approval: Yes) | 03.03.1998 | Communication of intention to grant the patent | 14.05.1998 | Fee for grant paid | 14.05.1998 | Fee for publishing/printing paid | Opposition(s) | 27.05.1999 | No opposition filed within time limit [1999/33] | Fees paid | Renewal fee | 22.09.1995 | Renewal fee patent year 03 | 21.09.1996 | Renewal fee patent year 04 | 15.09.1997 | Renewal fee patent year 05 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]EP0252609 (FUJITSU LTD [JP]) [A] 1,3,5 * the whole document *; | [A]US5182476 (HANNA JOHN E [US], et al) [A] 1,3,5 * abstract *; | [A]US4138649 (SCHAFFER GREGORY L) [A] * abstract *; | [A]US4450368 (SPENCE JOHN R [US]) [A] * abstract * | [A] - A. KANIEL, "Subtractor eliminates op - amp offset, common - mode errors", ELECTRONICS INT., (19780413), pages 135 - 137, XP001625250 [A] * figure 1A * |