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EP0613082
European procedure
Extract from the Register of European Patents
EP About this file: EP0613082
| EP0613082 - 4:2 adder and multiplier circuit employing the same [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 17.03.2001 Database last updated on 31.08.2024 | Most recent event Tooltip | 17.03.2001 | No opposition filed within time limit | published on 02.05.2001 [2001/18] | Applicant(s) | For all designated states NEC Corporation 7-1, Shiba 5-chome Minato-ku Tokyo 108-8001 / JP | [N/P] |
| Former [2000/19] | For all designated states NEC CORPORATION 7-1, Shiba 5-chome, Minato-ku Tokyo / JP | ||
| Former [1994/35] | For all designated states NEC CORPORATION 7-1, Shiba 5-chome Minato-ku Tokyo / JP | Inventor(s) | 01 /
Hagihara, Yasuhiko, c/o NEC CORPORATION 7-1, Shiba 5-chome Minato-ku, Tokyo / JP | [1994/35] | Representative(s) | Betten & Resch Patent- und Rechtsanwälte PartGmbB Postfach 10 02 51 80076 München / DE | [N/P] |
| Former [1994/35] | Betten & Resch Reichenbachstrasse 19 D-80469 München / DE | Application number, filing date | 94102668.4 | 22.02.1994 | [1994/35] | Priority number, date | JP19930031042 | 22.02.1993 Original published format: JP 3104293 | [1994/35] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0613082 | Date: | 31.08.1994 | Language: | EN | [1994/35] | Type: | B1 Patent specification | No.: | EP0613082 | Date: | 10.05.2000 | Language: | EN | [2000/19] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 07.06.1994 | Classification | IPC: | G06F7/50, G06F7/52 | [1999/10] | CPC: |
G06F7/509 (EP,US);
G06F7/5318 (EP,US);
G06F7/607 (EP,US)
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| Former IPC [1994/35] | G06F7/60, G06F7/52, G06F7/50 | Designated contracting states | DE, FR, GB [1994/35] | Title | German: | 4:2-Addierer und diesen verwendende Multiplizierschaltung | [1994/35] | English: | 4:2 adder and multiplier circuit employing the same | [1994/35] | French: | Additioneur 4:2 et circuit multiplieur utilisant celui-ci | [1994/35] | Examination procedure | 08.11.1994 | Examination requested [1995/02] | 08.06.1998 | Despatch of a communication from the examining division (Time limit: M06) | 04.12.1998 | Reply to a communication from the examining division | 23.02.1999 | Despatch of communication of intention to grant (Approval: No) | 23.08.1999 | Despatch of a communication from the examining division (Time limit: M02) | 13.10.1999 | Despatch of communication of intention to grant (Approval: later approval) | 13.10.1999 | Reply to a communication from the examining division | 04.11.1999 | Communication of intention to grant the patent | 14.02.2000 | Fee for grant paid | 14.02.2000 | Fee for publishing/printing paid | Opposition(s) | 13.02.2001 | No opposition filed within time limit [2001/18] | Fees paid | Renewal fee | 27.02.1996 | Renewal fee patent year 03 | 27.02.1997 | Renewal fee patent year 04 | 27.02.1998 | Renewal fee patent year 05 | 07.01.1999 | Renewal fee patent year 06 | 29.02.2000 | Renewal fee patent year 07 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X] - G. GOTO ET AL., "A 54 x 54-b Regularly Structured Tree Multiplier", IEEE JOURNAL OF SOLID-STATE CIRCUITS., NEW YORK US, (199209), vol. 27, no. 9, pages 1229 - 1235, XP000311186 [X] 1-7 * figures 1,4 * DOI: http://dx.doi.org/10.1109/4.149426 | [A] - M. SANTORO ET AL., "SPIM: A Pipelined 64 x 64-bit Iterative Multiplier", IEEE JOURNAL OF SOLID-STATE CIRCUITS., NEW YORK US, (198904), vol. 24, no. 2, pages 487 - 493, XP000124892 [A] 1,3,4,6 * page 489, column L, line 11 - line 13; table I * DOI: http://dx.doi.org/10.1109/4.18614 |