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Extract from the Register of European Patents

EP About this file: EP0631326

EP0631326 - Semiconductor memory device and method of manufacturing same [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  30.12.1999
Database last updated on 31.08.2024
Most recent event   Tooltip05.09.2008Change - representativepublished on 08.10.2008  [2008/41]
Applicant(s)For all designated states
ZAIDAN HOJIN HANDOTAI KENKYU SHINKOKAI
Kawauchi, Aoba-ku Sendai-shi
Miyagi-ken, 980 / JP
[N/P]
Former [1994/52]For all designated states
ZAIDAN HOJIN HANDOTAI KENKYU SHINKOKAI
Kawauchi, Aoba-ku
Sendai-shi, Miyagi-ken, 980 / JP
Inventor(s)01 / Nishizawa, Jun-ichi
6-16, Komegafukuro 1-chome, Aoba-ku
Sendai-shi, Miyagi-ken / JP
[1994/52]
Representative(s)Sparing Röhl Henseler
Postfach 14 04 43
40074 Düsseldorf / DE
[N/P]
Former [2008/41]Sparing Röhl Henseler Patentanwälte European Patent Attorneys
Postfach 14 04 43
40074 Düsseldorf / DE
Former [1994/52]Sparing - Röhl - Henseler Patentanwälte
Postfach 14 04 43
D-40074 Düsseldorf / DE
Application number, filing date94107261.310.05.1994
[1994/52]
Priority number, dateJP1993014712812.05.1993         Original published format: JP 14712893
[1994/52]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0631326
Date:28.12.1994
Language:EN
[1994/52]
Type: A3 Search report 
No.:EP0631326
Date:31.05.1995
Language:EN
[1995/22]
Type: B1 Patent specification 
No.:EP0631326
Date:24.02.1999
Language:EN
[1999/08]
Search report(s)(Supplementary) European search report - dispatched on:EP18.04.1995
ClassificationIPC:H01L29/86, H01L29/72, H01L21/329, H01L21/331
[1994/52]
CPC:
H01L29/66356 (EP,US); H01L27/08 (KR); H01L29/66196 (EP,US);
H01L29/739 (EP,US); H01L29/8616 (EP,US); H01L29/20 (EP)
Designated contracting statesDE,   FR,   GB [1994/52]
TitleGerman:Halbleiterspeicheranordnung und Verfahren zur Herstellung[1994/52]
English:Semiconductor memory device and method of manufacturing same[1994/52]
French:Dispositif de mémoire semi-conducteur et méthode de fabrication[1994/52]
Examination procedure26.05.1995Examination requested  [1995/30]
30.01.1997Despatch of a communication from the examining division (Time limit: M04)
05.06.1997Reply to a communication from the examining division
16.07.1998Despatch of communication of intention to grant (Approval: Yes)
18.08.1998Communication of intention to grant the patent
20.11.1998Fee for grant paid
20.11.1998Fee for publishing/printing paid
Opposition(s)25.11.1999No opposition filed within time limit [2000/07]
Fees paidRenewal fee
12.04.1996Renewal fee patent year 03
24.05.1997Renewal fee patent year 04
27.03.1998Renewal fee patent year 05
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[A]JPS61158184  ;
 [A]JPS60254777  ;
 [A]US3972059  (DISTEFANO THOMAS HERMAN);
 [A]DE2952513  (NIPPON MUSICAL INSTRUMENTS MFG);
 [A]US4484207  (NISHIZAWA JUN-ICHI [JP], et al);
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.